Hello, I am having trouble limiting the count on my binary counter. I can write a schematic, but no schematic should be necessary to explain the problem. The IC is SN74F163AN (see attached PDF) and the application is a clock.

I am trying to use the IC to count from 0 to 9 and then begin at 0 again. My clock input is a well-characterized 1Hz signal. The IC counts properly... I know this because I have a nixie tube and driver hooked up to it. I see it count up from 0-9, then blank out for 6 seconds because the tube can't display 10-15, and then start again at 0.

In spite of the binary settings (A-D), I cannot get the IC to limit the count to anything other than 0-15. As specified in the PDF, I have tried setting "LOAD" from low to high in order to program the inputs. (By the way, holding the "LOAD" on low displays the programmed value on the nixie tube.)

The rest of the settings are as follows: "ENP", "ENT", and "CLR" all high.

Note that I looked at the "RCO" output and found that it also always goes high at count 16.

Please let me know if I can provide any information. Thanks in advance for your help.

 

I think all you can do is load a start value and the count then increments from there to '15' and then back to '0' - unless you force another pre-emptive load using the RCO output.

I guess you could add additional logic to detect the '9' count which then clears the counter at the correct point (next clock pulse).

 

Thanks for the quick reply t_n_k.

" - unless you force another pre-emptive load using the RCO output."

I thought about this, but I'm not sure how to do this without some more circuitry. If the LOAD input required a high state in order to reprogram the start-point, I could just raise it when the RCO signal comes through (put a pull-down resistor between LOAD and ground and connect LOAD to RCO), but the way it's set up, I can't do this. (LOAD requires low to reprogram).

 

You need to use a 2-input NAND gate (74F37); its' inputs are from the 163 QA (pin 14) and QD (pin 11), the output of the NAND gets connected to LOAD\ (pin 9).

That way, LOAD\ is normally high when the counter is < 9. When the 9 count is reached, QA and QD are both high (binary 1001) so the output of the NAND gate goes low, enabling LOAD to occur on the next clock pulse. When the next clock occurs, the counter loads the A thru D inputs, which you should have set to all logic 0.

Note that there are quite a few 74 series NAND gates; many of them have open-collector outputs, which will require that you use a pull-up resistor. The '37 that I suggested has totem-pole outputs, so no resistor is required.

 

Why not just use a BCD counter instead - e.g CD4029

 

Ok, I will give that a try. I was afraid I would need one of those. I think I have a bunch of NAND gates sitting around from a teardown of an old oscilloscope. It might be a few days, but I will repost in this form once I try it out.

Thanks for the help!

 

Why not just use a BCD counter instead - e.g CD4029

Thanks for the heads up. I had originally purchased a bunch of counters from Digikey thinking one of them should work. Turns out I got a bunch like the SN74F163AN. The CD4029 definitely looks more appealing.

 

the 74x162 is a synchronous decade counter, which would do the job as well.

 

Thank you all for your help. I tried out the NAND gate. It worked just as you specified. Here is proof.

Thanks again!