Hello again friends
I've been fiddling with a circuit that I just cannot get to work properly for reasons I don't understand.

Basically I want the source of M2 to produce a clean 150v regardless of current flowing through the load (R2)
The inverting input of the opamp has 7.5v via the voltage divider and I used a 1/20 ratio divider for the feedback from the output of the source follower at the load which I fed into another source follower so the feedback loop doesn't leak current on me.
7.5v X 20 = 150v in theory

The goal of this design is to regulate the load without using a HV opamp so the output of the opamp is feeding an amplifier to separate the voltages.
The problem is it just doesn't work on the breadboard. It works in spice just not on the breadboard.
The opamps output sits at around -1 to 2v and therefore output of M2 sits near B+.
Any clue why it's not working as it should?

 

Hello again friends
I've been fiddling with a circuit that I just cannot get to work properly for reasons I don't understand.
View attachment 129622
Basically I want the source of M2 to produce a clean 150v regardless of current flowing through the load (R2)
The inverting input of the opamp has 7.5v via the voltage divider and I used a 1/20 ratio divider for the feedback from the output of the source follower at the load which I fed into another source follower so the feedback loop doesn't leak current on me.
7.5v X 20 = 150v in theory

The goal of this design is to regulate the load without using a HV opamp so the output of the opamp is feeding an amplifier to separate the voltages.
The problem is it just doesn't work on the breadboard. It works in spice just not on the breadboard.
The opamps output sits at around -1 to 2v and therefore output of M2 sits near B+.
Any clue why it's not working as it should?

On the surface it seems like you could eliminate M1 and the negitive supply for the op amp.
It will need some frequency compensation would be my second guess.
Could you post your .asc files?
Would you mind using BJT instead of FETs?

 

I need M1 because the I don't want current to leak into the feedback loop.
Getting rid of the negative supply would be fine unless I use BJTs probably.
I'm not sure what you mean by frequency compensation.
I would try BJTs but I don't have any NPNs lying around that can handle this voltage.
I attached the ASC file, for some reason the simulation oscillates with the mosfets but I previously used BJTs and it worked fine. In either case the DC voltages are where they are supposed to be unlike the real life verison.

 

I think the highest voltage NPNs I have use 80v, I could just cascode them to meet the voltage standards. Is there a reason they may perform better?

 

The circuit has several issues. You are trying to design a HV regulator. The feedback loop needs to be a precise ratio of the output level, so the uncontrolled gain of M1 has got to go. The circuit also needs to compare this voltage against a reference to drive the control loop into compliance. I suggest spending some time reading up on voltage regulators.

It sounds like you want the control loop isolated from the HV source, this can certainly be done but it still needs to be a precise ratio of the actual output voltage.

 

I think the highest voltage NPNs I have use 80v, I could just cascode them to meet the voltage standards. Is there a reason they may perform better?

Here is a circuit I stole from @tindel.

 

The feedback loop needs to be a precise ratio of the output level, so the uncontrolled gain of M1 has got to go.

Precise voltage isn't an issue, I can just adjust the feedback ratio.
I don't understand what you mean about the "gain" of M1, it has no gain.

The circuit also needs to compare this voltage against a reference to drive the control loop into compliance. I suggest spending some time reading up on voltage regulators.

It is referenced to a voltage..

Here is a circuit I stole

I don't see how that circuit is effectively any different than mine.

 

I took a few liberties in modifying your circuit as shown below.

I removed M1 as it was not needed.
Added C1, R3 and R4 for loop compensation
This compensation eliminates the loop phase shift that otherwise will cause oscillations.
Changed the value of R8 to give 150V out.
Removed R10 as it served no useful purpose.
Increased the value of R6 to reduce bias current.
C2 should be smaller than 1 farad.

I also added source V2 for simulation testing of the loop stability.
It's generating a 100mV pulse into the loop to show the transient response.
It looks fine with no significant overshoot or ringing at the pulse edges.
Without the compensation, it oscillated.

V2 is also an AC source to do an AC analysis and generate a Bode plot of gain and phase-shift versus frequency, shown in the second attachment.
It looks fine with no peak in the gain.
Without the compensation, there's a large peak in the output gain at about 7MHz, indicating loop instability.

I didn't have the model for your MOSFET, so I had to use a different one, but that shouldn't have a big effect on the results.

If your real life circuit sill doesn't work after these mods, double check all the wiring and transistor pinouts.

 

Your attachments don't show
"NVM works now "

 

I probably was in the process of doing some editing.

 

Yay that worked! Thanks!
I'm trying to understand where I went wrong, the main effective difference between mine and yours is that compensation on the transistor.
Could oscillation have caused such a DC error?

 

I'm trying to understand where I went wrong, the main effective difference between mine and yours is that compensation on the transistor.

Anytime you add any gain inside the feedback loop of an op amp, (in this case by M3) there's a high chance of oscillations.
You thus need to compensate for that to rolloff the gain and frequency response such that there is never positive feedback (combination of loop gain and phase-shift) at any frequency that could cause instability or oscillation.

Could oscillation have caused such a DC error?

It's possible I suppose.
Do you have an oscilloscope to view the signals?

 

See

 

See

Nice, simple circuit.
You can, of course, generate the V1 bias voltage from a resistive divider off the HV DC supply.

 

Nice, simple circuit.
You can, of course, generate the V1 bias voltage from a resistive divider off the HV DC supply.

I agree, but the Zener diode is 30 times better!

 

Can someone explain that circuit to me? U1 is a thyristor right? I don't know much about them.

 

Can someone explain that circuit to me? U1 is a thyristor right? I don't know much about them.

No U1 is a zener diode TL431, programmed with the resistors R2,3

 

Can someone share the spice model for that? I can't seem to get mine to work.

 

U1 has a 2.5v reference voltage with a built-in dedicated op amp.
Here's the equivalent circuit from its data sheet:

When the REF input voltage reaches the Vref voltage of 2.5V, the amp turns on the transistor, which starts conducting current between the CATHODE and ANODE.
Normally there is a resistor (or other current limiting circuit) between the V+ supply and the CATHODE to limit the current when the transistor starts to conduct.

For example, with a resistor in the CATHODE circuit and REF connected to the CATHODE as below, the circuit acts as a shunt regulator, with the voltage at the CATHODE will remaining constant at 2.5V, within the current limits of the transistor.

If you add a resistive divider as below, then the output voltage, Vka, will be a function of the divider resistor values:

In Bordodynov's circuits, the current Ika controls transistor Q1/M1, configured in a grounded base/gate configuration, to regulate the output voltage per the voltage divider resistors R2 and R3.

 

Here are the files I use.
Put the .asy file in lib/sym/References directory.
Put the .lib file in the lib/sub directory.