Bear in mind that it is not unusual to use resistors with ±5% tolerance. Hence your Example 2 is good enough in this case.

 

Your original circuit was wrongly biased very close to saturation which caused severe clipping to the bottoms of the collector output waveform.
Also since the Rc and Re had almost the same resistances then the voltage gain below clipping levels was only about 1.
I use Microsoft Paint program to copy, label and paste schematics.

Hee, hee. I am 78 years old and healthy enough that all my parts work fine.

 

Your original circuit was wrongly biased very close to saturation which caused severe clipping to the bottoms of the collector output waveform.
Also since the Rc and Re had almost the same resistances then the voltage gain below clipping levels was only about 1.
I use Microsoft Paint program to copy, label and paste schematics.

Hee, hee. I am 78 years old and healthy enough that all my parts work fine.

I am encouraged! I noticed today that my base bias voltage Vb sets the max swing the circuit can tolerate from the siggen. For example, with Vb = 1.35 volts, clipping of the input will occur for any input signal from the siggen exceeding 2.7 volts peak to peak.

I'm doing this to make sure I understand voltage divider biasing correctly. Right now, I feel like a 'man with a fish' from the old saying "you can feed a man a fish, or you can teach him how to fish"

My DC power supply can attain 120vdc, at 20 amps, and I tried establishing a Vb of 4 volts, leading to a Ve of (4 - 0.7) = 3.3 volts, and I cannot get a decent voltage gain Rc/Re. My intent was to allow a 7 volt peak-to-peak input to the base. A Vb = 4vdc would allow that. Surely there is some combination of Vcc and the four resistors that would allow a Vb = 4vdc.

So the rust has clogged my memory banks and I will keep at it. Since my power supply is more than capable, and my siggen is too, I feel I should be able to say "I'm setting this up for a 4vdc base bias", the voltage across R2 - IF I actually understand things enough. So far, I cannot make the numbers work, in terms of getting an Rc/Re voltage gain of 10.

 

You are going about this in the wrong way.

Let's say your input voltage is 2.4V peak to peak, that is, an amplitiude of 1.2V.
A gain of 10 would bring the amplitude to 12V, or 24V peak to peak.
Why do you want a signal amplitude of 12V?
What kind of load are you driving?
What is the impedance of the load?
What is the power output delivered to the load?

If you are attempting to build a power amplifier, it is not done with a single stage, single transistor amplifier.
It usually takes three stages in a design of a power amplifier.

Stage 1 - A preamp provides voltage gain from a high impedance source, e.g. 10mV to 1V amplitude requires a voltage gain of 100.

Stage 2 - A driver stage from the low impedance output of the preamp to a low impedance input of the power amp stage. A modest gain of 5 to boost the signal to 5V plus some current drive, e.g. 500mA

Stage 3 - A power output stage with low output impedance, e.g. less than 1Ω. What you need is high current output. For example, if the amplifier has to drive 100W into an 8Ω loudspeaker, then you would need output drive capability of about 4A @ 30V.

The bottom line is, you need to pay attention to the current and voltage requirements at every stage as well as input and output impedance.

 

You are going about this in the wrong way.

Let's say your input voltage is 2.4V peak to peak, that is, an amplitiude of 1.2V.
A gain of 10 would bring the amplitude to 12V, or 24V peak to peak.
Why do you want a signal amplitude of 12V?
What kind of load are you driving?
What is the impedance of the load?
What is the power output delivered to the load?

If you are attempting to build a power amplifier, it is not done with a single stage, single transistor amplifier.
It usually takes three stages in a design of a power amplifier.

Stage 1 - A preamp provides voltage gain from a high impedance source, e.g. 10mV to 1V amplitude requires a voltage gain of 100.

Stage 2 - A driver stage from the low impedance output of the preamp to a low impedance input of the power amp stage. A modest gain of 5 to boost the signal to 5V plus some current drive, e.g. 500mA

Stage 3 - A power output stage with low output impedance, e.g. less than 1Ω. What you need is high current output. For example, if the amplifier has to drive 100W into an 8Ω loudspeaker, then you would need output drive capability of about 4A @ 30V.

The bottom line is, you need to pay attention to the current and voltage requirements at every stage as well as input and output impedance.

I don't have any design goal, I'm trying to make sure I have a firm grasp of how to do the biasing, nothing more. My purpose in saying "I want to drive this linear amplifier with a 7vpp input sine wave" is because if I could do that, my confidence that I really understand the biasing would greatly improve.

I'm trying to answer the question "if I want to require a 4vdc base bias, do I understand biasing enough now to do that?"

It seems like a reasonable expectation of myself:
- my voltage power supply maxes out at 120vdc and 20 amps
- my siggen maxes out at 20vpp
- the 2N3094 is capable of much higher Vce than 5 volts

So I chose an arbitrary test, "let's set Vb, the base bias, to 4 volts to make sure I understand the biasing"

If you have 'mental dexterity' with a technical issue, presenting a reasonable challenge to yourself is doable. I don't have such dexterity yet as I proved to myself.

I'm feeling sort of stupid but that's okay, I can proceed through that. I know for a fact that a week from now the self-recriminations might be harsh but no big deal, I love electronics, it's a great hobby.

 

Ok. Driving a BJT amplifier with 7V peak to peak is unrealistic. Here is why.

The base-emitter junction looks like a P-N junction diode. The I-V characteristic curve looks something like this.




The P-N junction does not start to conduct until the forward voltage is about 0.6V. After about 0.8V the current rises rapidly.
Hence a forward bias voltage between 0.65V and 0.70V is commonly used as a rough guide.

Thus, it only takes about 0.2V peak-to-peak to drive the transistor from cutoff to saturation.

 

If you would like to experiment with some simple BJT amplifier circuits, try these two.

In the first circuit on the left, base bias is provided directly from the positive supply rail. This configuration is not recommended because it can drift with temperature. The second circuit on the right applies negative feedback to the base. This circuit is more stable than the first. The voltage gain is about 50 for the first and 30 for the second.

 

If you would like to experiment with some simple BJT amplifier circuits, try these two.

In the first circuit on the left, base bias is provided directly from the positive supply rail. This configuration is not recommended because it can drift with temperature. The second circuit on the right applies negative feedback to the base. This circuit is more stable than the first. The voltage gain is about 50 for the first and 30 for the second.

View attachment 305623

Thank you!

 

I'm doing this to make sure I understand voltage divider biasing correctly. Right now, I feel like a 'man with a fish' from the old saying "you can feed a man a fish, or you can teach him how to fish"
My DC power supply can attain 120vdc, at 20 amps, and I tried establishing a Vb of 4 volts, leading to a Ve of (4 - 0.7) = 3.3 volts, and I cannot get a decent voltage gain Rc/Re.

Just to avoid misunderstandings: Which values for R1, R2 and Re are you speaking about?

..... I feel I should be able to say "I'm setting this up for a 4vdc base bias", the voltage across R2 - IF I actually understand things enough. So far, I cannot make the numbers work, in terms of getting an Rc/Re voltage gain of 10.

Did you read my contribution in post#20 ? Are you aware that the expression Rc/Re is a - more or less - rough approximation only (depending on the transconductance gm resp. the DC current Ic) ?

 

Generally the first things in designing an amplifier stage is deciding the gain required. Next comes an estimation of the amplitude of the input signal, although it may be more important to set the output amplitude. and know the load impedance. Setting the base bias is much farther down the list, because that depends on other variables.
Certainly the base bias is important, but it depends on many other variables.

 

The P-N junction does not start to conduct until the forward voltage is about 0.6V. After about 0.8V the current rises rapidly.
Hence a forward bias voltage between 0.65V and 0.70V is commonly used as a rough guide.

Yes - and such "rough guide" is mostly appropriate and sufficient if (and only if) the circuit under discussion has enough negative DC feedback, e.g. provided by an emitter resistor Re.

Example: With an emitter resistor Re=1kohms any uncertainty/variation of 0,7-0,65=0.05 volts will cause a collector current variation/tolerance of app 0.05/1k=0.05mA only - equivalent to 5% for a nominal value Ic=1mA.

 

I am going to take you through the entire design of a single transistor, common emitter amplifier with the following characteristics.

Input: 7Vp-p or 3.5 V peak

Output 14V p-p, gain of two

For the input voltage at the base to swing + and – 3.5V, the bias point emitter voltage must be at least 3.5V. We will use 4.0V.

Ve: 4.0V

Now let’s determine Vcc, the supply voltage.

The collector must swing + and – 7V. At the bias point, it needs to be at least 7V from Vcc. And we need the transistor to drop a similar voltage. In cutoff, the collector voltage will be Vcc. In saturation it will be 1/3 of Vcc since it will form a divider with the emitter resistor, which is half the collector resistor for a gain of 2. So we need at least 14V / (2/3) = 21V. But we don’t want the transistor anywhere near cutoff or saturation, so we will add a bit to the Vcc. I choose 24V.

Vcc: 24V

Now we need to set a bias current. To do this right you would look at the characteristic curves of the transistor and determine a point that would allow the needed swing in voltage at the collector while staying in the linear region. But, from experience, I choose 5ma as a reasonable bias current for the 2N3904.

Now we can calculate the collector resistor. We want it to drop 7V + the extra headroom of 2V. So, it needs to drop 9V at 5mA. Use Ohm’s law, R = V / I = 9 / 0.005 = 1800 Ohms.

Rc: 1800 Ohm

And the emitter resistor is half that to get a gain of two.

Re: 900 Ohm

And now we need to calculate the biasing resistors. We need 4V at the emitter, so 4.65V at the base, using 0.65 as the typical voltage drop of the BE junction at that kind of current.

So, we are going to divide 24V to get 4.65. So the ratio of the two resistors is 4.65/24 = 0.19.

The magnitude of the resistors is chosen based on the needed base current. We look up the Beta of the 2N3904 at 5mA collector current and it is about 150. So the bias current is going to be about 5mA / 150 = 33uA. We want to make sure we have enough current so double that, in case the beta is low, to 66uA.

Ib: 66uA

Now we want to make a voltage divider that is not affected much by the base current, so we choose a current 10 times higher.

Ibias = 660uA


The total resistance of the divider then must be 24V divided by the bias current.

Rbias: 24 / 0.00066 = 36363.


And the lower bias resistor has to be .19 times that to get the right bias voltage.

Rlow = 36363 * 0.19 = 6908

And the high bias resistor is just the total minus the low one.

Rhigh = 36363 – 6908 = 29455.


Here is a simulation:



And the FFT shows a distortion of only 0.6%, which is not bad for this simple an amplifier. None of the voltages are exactly as calculated, but my conservative choices made it work very reasonably.

Full disclosure: I did not do this well with my initial calculations. I was not taking into effect the needed emitter voltage and the necessity to keep the transistor far from cutoff. But my simulations informed me, and after the learning, I calculated these values from scratch. And it just worked.

Edited to add: The clipping point is about 8V p-p, so again, adding the extra voltage to the supply voltage and bias point worked out very well. Always be conservative in you designs.

 

Ok. Driving a BJT amplifier with 7V peak to peak is unrealistic. Here is why.

The base-emitter junction looks like a P-N junction diode. The I-V characteristic curve looks something like this.

View attachment 305622


The P-N junction does not start to conduct until the forward voltage is about 0.6V. After about 0.8V the current rises rapidly.
Hence a forward bias voltage between 0.65V and 0.70V is commonly used as a rough guide.

Thus, it only takes about 0.2V peak-to-peak to drive the transistor from cutoff to saturation.

But the transistor has an emitter resistor that uses up one-third of the output voltage swing and adds it to the base voltage swing. It is called negative feedback and it reduces the gain and reduces the distortion.

 

Ok. Driving a BJT amplifier with 7V peak to peak is unrealistic. Here is why.

That all applies if there is no negative feedback. See my design in the post #32.

The input voltage is 7V p-p. The voltage at the base makes that full 7V excursion. But, due to negative feedback, the emitter also swings by nearly that amount. The Vbe varies only in the range of 627 to 710 mV.

 

That all applies if there is no negative feedback. See my design in the post #32.

The input voltage is 7V p-p. The voltage at the base makes that full 7V excursion. But, due to negative feedback, the emitter also swings by nearly that amount. The Vbe varies only in the range of 627 to 710 mV.

True. But the TS never stated how much voltage gain was required.
With a gain of just 2, lots of negative feedback is require to bring the output down to 14V peak-to-peak, with a 24V supply voltage. TS started off with a supply voltage of 10V. To the TS, details matter.

 

True. But the TS never stated how much voltage gain was required.
With a gain of just 2, lots of negative feedback is require to bring the output down to 14V peak-to-peak, with a 24V supply voltage. TS started off with a supply voltage of 10V. To the TS, details matter.

Which is why I explained every decision and calculation I made.

With 10V the gain could not even be one, at least not with an emitter resistor setting it.

He asked how to do the design, and that is what showed him.

 

Now let’s determine Vcc, the supply voltage.

The collector must swing + and – 7V. At the bias point, it needs to be at least 7V from Vcc. And we need the transistor to drop a similar voltage. In cutoff, the collector voltage will be Vcc. In saturation it will be 1/3 of Vcc since it will form a divider with the emitter resistor, which is half the collector resistor for a gain of 2. So we need at least 14V / (2/3) = 21V.

Excellent guidance, thank you. One point of confusion for me was "In saturation it will be 1/3 of Vcc since it will form a divider with the emitter resistor, which is half the collector resistor for a gain of 2"

My memory is that in saturation, Vc, the collector voltage, goes to zero, not 1/3 of Vcc.
I could not figure out the "14 / (2/3)" part.

 

Excellent guidance, thank you. One point of confusion for me was "In saturation it will be 1/3 of Vcc since it will form a divider with the emitter resistor, which is half the collector resistor for a gain of 2"

My memory is that in saturation, Vc, the collector voltage, goes to zero, not 1/3 of Vcc.
I could not figure out the "14 / (2/3)" part.

It's not the collector voltage that goes to zero (or, in real life, a small positive voltage), but rather the collector-emitter voltage, Vce.

Since the emitter current is about equal to the collector current and since the collector resistor is twice the size of the emitter resistor, whatever voltage is dropped across the emitter resistor will result in twice that much voltage being dropped across the collector resistor. Since the total supply voltage has to equal the sum of the voltages dropped across the collector resistor, the transistor, and the emitter resistor, when the emitter resistor is dropping 1/3 of the total supply voltage, the collector resistor is dropping 2/3 of it, leaving nothing left to be dropped across the transistor's collector-emitter terminals.

Let's walk through the math, step by step.

The emitter voltage is Vee (because that's what the bottom of the emitter resistor is tied to, which happens to be 0 V in this case) plus Ie·Re.

The collector voltage is Vcc (because that is what the top of the collector resistor is tied to) minus Ic·Rc.

The collector-emitter voltage is

Vce = Vc - Ve = (Vcc - Ic·Rc) - (Vee + Ie·Re)

The emitter voltage is always

Ve = Vb - Vbe

Therefore, the emitter current is given by

Ie = (Ve - Vee) / Re = (Vb - Vbe - Vee) / Re

In the active region, Vbe is roughly constant at about 0.7 V. In the linear region, we often assume that the transistor beta is high enough that we can consider the collector and emitter currents to be the same. This assumption falls apart as you get toward saturation, but we can often get a useful rough result by ignoring this.

Similarly, real transistors saturate before Vce gets all the way to 0 V, but we can usually get a decent first estimate by ignoring this since typical saturation voltages are in the 50 mV to 300 mV range.

So, with these two simplifications, we have

Vce = (Vcc - Ic·Rc) - (Vee + Ie·Re)
Vce ~= (Vcc - Ie·Rc) - (Vee + Ie·Re)
Vce ~= (Vcc - Vee) - Ie(Rc + Re)

Notice that (Vce - Vee) is the total supply voltage and Ie(Rc _ Rc) is the portion of that voltage that is dropped across the two resistors.

We also have, above, the expression for Ie in terms of Vb and can substitute that in:

Vce ~= (Vcc - Vee) - [(Vb - Vbe - Vee) / Re](Rc + Re)

Vce ~= (Vcc - Vee) - (Vb - Vbe - Vee)(Rc/Re + 1)

The only variable here is Vb, since we can assume Vbe is about 0.7 V.

Vce ~= (Vcc - Vee) - Vb(Rc/Re + 1) + (Vbe + Vee)(Rc/Re + 1)

Solving for Vb, we get:

Vb(Rc/Re + 1) ~= (Vcc - Vee) + (Vbe + Vee)(Rc/Re + 1) - Vce

Vb ~= (Vcc - Vee)/(Rc/Re + 1) + (Vbe + Vee) - Vce/(Rc/Re + 1)

This give you the approximate value of Vb for an arbitrary Vce (provided the transistor is in the active region).

For the point at which it saturates, we set Vce to the saturation voltage, Vcesat, which is often taken to be 0:

Vb ~= (Vcc - Vee)/(Rc/Re + 1) + (Vbe + Vee)

In your case, Vee = 0 V, so this simplifies even more:

Vb ~= Vcc/(Rc/Re + 1) + Vbe

In BobTPH's circuit, Rc = 1800 Ω and Re = 900 Ω, so Rc/Re = 2 and (Rc/Re + 1) = 3

So you end up with

Vc = (10 V / 3) + 0.7 V = 4 V.

As being, approximately, the base voltage that puts the transistor into saturation. It will actually occur as a slightly lower voltage.

 

It's not the collector voltage that goes to zero (or, in real life, a small positive voltage), but rather the collector-emitter voltage, Vce.
.

Blows me away, I aspire to your level of comprehension; I don't quite grok all that but as I refresh my memory I find I can go back and re-read and I process things better.

I assembled BobTPH's circuit after reading, and mostly understanding, what he said.

I'm still getting distortion on the output but it looks closer to a sine wave than prior efforts. I checked my oscilloscope input impedance to make sure it was not low enough to affect the circuit; the manual says "1MΩ±2% in parallel with 20pF±3pF"
so I'm thinking I'm okay there.

I fed the siggen to the base through a 1uF cap (instead of the .1uF I used previously), giving an Xc of 1 / (2piF(1uF)) = 0.16 ohms of Xc because I'm using 1Mhz. Checking the input at the base after it passes through the cap looks like a sine wave; the output is not there yet.

My expectation of a Class A behavior is reasonable, I think, and a clean sine wave is what I'm after, and I have to keep at it.

 

What is the amplitude of the output from the signal generator?

What is it's output impedance? 50 Ω and 600 Ω are common.

It sounds like you might really benefit by taking a step back and getting comfortable with the basics of DC circuit analysis (which is all I was using in my prior post). Unless and until you do that, you will be really struggling to make headway and those struggles will really hinder your ability to see and grasp the concepts behind struggles with the fundamentals.