I'm trying to get a clean sine wave output from a very simple voltage divider biasing for an NPN 2n3904 BJT.

I set a Vcc = 10vdc. I selected the resistors (R1, R2, Re, Rc) to achieve a 5vdc midpoint bias at the collector, the 'Q' point when no AC signal is supplied to the base. So far so good, I verified with my DVM and with a scope that with no input to the base from my siggen, my collector is at about 5vdc, and the Vbe is about 0.7vdc. The transistor is on, and it is not saturated, it is at 5vdc on the collector, so the input sine wave (4vpp) should swing about a 5vdc level.

I turn on the siggen and get a clean sine wave at the base but a distorted (not clipped, just not a sine wave) output at the collector.

I am suspecting a bad 2N3904 NPN but before I buy new ones, was wondering if anyone knows of a fault of some kind that would lead a BJT to create a non-sine wave on the output. This is not a clipped output distortion at the collector - the signal looks like a positive 1/2 cycle with another, slightly higher voltage positive 1/2 cycle, then repeats that shape. Since the base is seeing a clean sine wave, and the collector Q point is 5vdc with 10v for Vcc, I'm not understanding why the midpoint biasing is failing to give me a clean sine wave output. I'm stumped.

My oscilloscope shows the correct frequency. I've tried frequencies from 1Khz to 1Mhz with no change: weird non-sine wave output.

I've tried more than one value for Vcc and for the set of biasing resistors and I cannot get this BJT to produce a clean sine wave output.
I've tried using a blocking capacitor between the siggen and base, and without a blocking cap, no difference. The sine wave from the
siggen is perfect at the base, in both cases.

 

I'm trying to get a clean sine wave output from a very simple voltage divider biasing for an NPN 2n3904 BJT.

I set a Vcc = 10vdc. I selected the resistors (R1, R2, Re, Rc) to achieve a 5vdc midpoint bias at the collector, the 'Q' point when no AC signal is supplied to the base. So far so good, I verified with my DVM and with a scope that with no input to the base from my siggen, my collector is at about 5vdc, and the Vbe is about 0.7vdc. The transistor is on, and it is not saturated, it is at 5vdc on the collector, so the input sine wave (4vpp) should swing about a 5vdc level.

I turn on the siggen and get a clean sine wave at the base but a distorted (not clipped, just not a sine wave) output at the collector.

I am suspecting a bad 2N3904 NPN but before I buy new ones, was wondering if anyone knows of a fault of some kind that would lead a BJT to create a non-sine wave on the output. This is not a clipped output distortion at the collector - the signal looks like a positive 1/2 cycle with another, slightly higher voltage positive 1/2 cycle, then repeats that shape. Since the base is seeing a clean sine wave, and the collector Q point is 5vdc with 10v for Vcc, I'm not understanding why the midpoint biasing is failing to give me a clean sine wave output. I'm stumped.

My oscilloscope shows the correct frequency. I've tried frequencies from 1Khz to 1Mhz with no change: weird non-sine wave output.

I've tried more than one value for Vcc and for the set of biasing resistors and I cannot get this BJT to produce a clean sine wave output.
I've tried using a blocking capacitor between the siggen and base, and without a blocking cap, no difference. The sine wave from the
siggen is perfect at the base, in both cases.

Welcome to AAC!

Schematic drawing is the language of electronics. We have no idea of what your circuit looks like or what value resistors you used. Show us the schematic with resistance values included.

 

I'm trying to get a clean sine wave output from a very simple voltage divider biasing for an NPN 2n3904 BJT.

I set a Vcc = 10vdc. I selected the resistors (R1, R2, Re, Rc) to achieve a 5vdc midpoint bias at the collector, the 'Q' point when no AC signal is supplied to the base. So far so good, I verified with my DVM and with a scope that with no input to the base from my siggen, my collector is at about 5vdc, and the Vbe is about 0.7vdc. The transistor is on, and it is not saturated, it is at 5vdc on the collector, so the input sine wave (4vpp) should swing about a 5vdc level.

I turn on the siggen and get a clean sine wave at the base but a distorted (not clipped, just not a sine wave) output at the collector.

I am suspecting a bad 2N3904 NPN but before I buy new ones, was wondering if anyone knows of a fault of some kind that would lead a BJT to create a non-sine wave on the output. This is not a clipped output distortion at the collector - the signal looks like a positive 1/2 cycle with another, slightly higher voltage positive 1/2 cycle, then repeats that shape. Since the base is seeing a clean sine wave, and the collector Q point is 5vdc with 10v for Vcc, I'm not understanding why the midpoint biasing is failing to give me a clean sine wave output. I'm stumped.

My oscilloscope shows the correct frequency. I've tried frequencies from 1Khz to 1Mhz with no change: weird non-sine wave output.

I've tried more than one value for Vcc and for the set of biasing resistors and I cannot get this BJT to produce a clean sine wave output.
I've tried using a blocking capacitor between the siggen and base, and without a blocking cap, no difference. The sine wave from the
siggen is perfect at the base, in both cases.

This is almost like telling someone telling you that they have a car and although they put gas in it, it won't start and expecting you to be able to give them useful feedback on why not. For all you know, the car doesn't have a battery in it or by putting gas in it they meant they put a can of gas in the trunk. With so little information, you are very likely to make assumptions about what they did or did not do that are at complete odds with reality.

We really need a schematic in order to know exactly what circuit you are talking about? Without that, we just guessing. In particular, we have NO idea what the nominal gain of your circuit is, what the impedance of your bias network is, how you are coupling the signal from the generator to the circuit, what the values are of any coupling capacitors you are using, what the frequency cutoff limits are for your circuit. In short, virtually nothing.

 

I don't have a circuit-drawing tool but voltage divider bias is well known:

1) R2 from base to ground - current iteration using 1Kohms
2) R1 from Vcc to base - 1Kohms in current iteration of the circuit
3) Rc from Vcc to the collector - 975 ohms in present iteration of the circuit
4) Re from emitter to ground - 800 ohms in present iteration
5) Vcc is 10vdc in the present circuit
6) I've tried with and without a bypass cap .1 uFd across the emitter resistor, and as a blocking cap between the siggen and the base, with absolutely no change to the distorted output signal.

It just seems to me that if the Q point is midway biased at 5vdc, then the 2vpp siggen input should swing cleanly, up and down across the 5vdc Q point, at least that was my expectation.


This is the circuit - the voltage divider bias example below is the standard way, and the one I followed.
I'm using a 2n3904 NPN for the BJT. Keep in mind the current resistor values are just the most recent iteration and I can easily change them. I started with a DC biasing line of reasoning from https://www.petervis.com/GCSE_Desig...Potential_Divider/Potential_Divider_Bias.html - that was my starting point.

The current iteration is just an attempt, and despite all biasing efforts, the same disfigured signal output shows up.

 

My first suggestion is using a coupling capacitor so that the resistance of the signal generator will not affect the base bias. my secoond suggestion is start with a much smaller signal, about 0.01 volts, and check for distortion. Then increase the signal a bit. Not all transistors are linear under all operating conditions. so starting small will be the way to begin.

 

Your resistor values are way off anything close to being practical.
You have a voltage gain of close to unity.
Your input impedance is too low.

 

Your resistor values are way off anything close to being practical.
You have a voltage gain of close to unity.
Your input impedance is too low.

The hFE was 100 to 300 on the datasheet but am wondering how to determine the unity voltage gain you're seeing. Also, the input impedance is greater than 50 ohms (R2 and R1 are both 1K ohm resistors).

Per MisterBill2's suggestion, I tried a slow ramp-up from the siggen and the distortion remains unless I drop it to 1vpp (the DC blocking cap was already there btwn the siggen and the circuit, and I actually removed it at one point to assess any change, and saw none).

At 1vpp, the sine wave is clean at the collector.

I'm 64yo and haven't done this kind of thing since 1982 and it is coming back quite slow, surprisingly. I switched to software in 1987 and must have forgotten too much.

It is a cool hobby to come back to, for sure.

 

Here is an LTspice simulation plotting three different resistor values in the place of R4 (1k, 10k, 100k). The simulation also sweeps the input voltage from 0-10V to show at which point the transistor begins to turn on for each resistor. We see that the transistor is in active mode with the 1k resistor, is barely turned on but still in active mode with the 10k resistor and is in cutoff mode with the 100k resistor.

 

Here is an LTspice simulation plotting three different resistor values in the place of R4 (1k, 10k, 100k). The simulation also sweeps the input voltage from 0-10V to show at which point the transistor begins to turn on for each resistor. We see that the transistor is in active mode with the 1k resistor, is barely turned on but still in active mode with the 10k resistor and is in cutoff mode with the 100k resistor.

View attachment 305548

Thank you kindly - I will try those resistor values. I have heard of LTSpice but have no experience with it. It looks great.

 

Here are steps in order to design an NPN BJT common emitter amplifier.

1) Select the operating supply voltage, e.g. Vcc = 10V
2) Select the collector load resistance, e.g. R3 = 1kΩ
3) Select the voltage gain, e.g. Av = -10 (negative to show that its an inverting amplifier)
4) R3/R4 = -Av, hence R4 = 1000Ω/10 = 100Ω
5) Select the input impedance, e.g. R2 = 4.7kΩ
6) Adjust R1/R2 ratio to give desired DC bias, e.g. R1 = 30kΩ

 

Here are steps in order to design an NPN BJT common emitter amplifier.

1) Select the operating supply voltage, e.g. Vcc = 10V
2) Select the collector load resistance, e.g. R3 = 1kΩ
3) Select the voltage gain, e.g. Av = -10 (negative to show that its an inverting amplifier)
4) R3/R4 = -AV, hence R4 = 1000/10 = 100Ω
5) Select the input impedance, e.g. R2 = 4.7kΩ
6) Adjust R1/R2 ratio to give desired DC bias, e.g. R1 = 30kΩ

View attachment 305549

Just fantastic, thank you kindly. One question about point (6): R1 / R2 = 30k / 4.7k = 6.38. In other words, R1 is 6.38 times greater resistance than R2. My first instinct is:

- that means the voltage at the top of R2, ie. the base bias voltage, will be 10v - 6.38 = 3.62vdc, because R1 will drop 6.38vdc. How would I know, though, that is the correct base bias voltage?

I am very clumsy here with not being able to remember, I apologize if I seem naive, but I think once I get back into it, I will remember more.

 

Thank you kindly - I will try those resistor values. I have heard of LTSpice but have no experience with it. It looks great.

Use an LED in place of one of the resistors R1-R3 to see what happens. The circuit is current limited so you won't ruin anything. Measure the voltage across each node to see how this corresponds to changes at the collector and emitter as you sweep the input voltage and remember BJTs are current controlled devices.

 

Just fantastic, thank you kindly. One question about point (6): R1 / R2 = 30k / 4.7k = 6.38. In other words, R1 is 6.38 times greater resistance than R2. My first instinct is:

- that means the voltage at the top of R2, ie. the base bias voltage, will be 10v - 6.38 = 3.62vdc, because R1 will drop 6.38vdc. How would I know, though, that is the correct base bias voltage?

I am very clumsy here with not being able to remember, I apologize if I seem naive, but I think once I get back into it, I will remember more.

I take it back. It's 10 volts being dropped across (R1 + R2) => (10v) / 34700 ohms = 0.288mA
Voltage at top of R2 is thus (0.288)(4700) = 1.35 volts

Is there a way for me to know that this is correct? Obviously 1.35vdc - 0.7vdc = 654mV on top of the emitter resistor, and I could determine the emitter resistor voltage drop via use of Ic.

Is that the key in choosing the base bias voltage? ie.
1) know Ic
2) calculate Vr4 based on Ic and the previously-established values of R3 and R4
3) add: Vr4 + 0.7v
4) the base bias voltage Vb should be just above that,
5) now use the R1/R2 ratio and the Vb target to select R2

Is that how to select the base bias voltage?

 

Just fantastic, thank you kindly. One question about point (6): R1 / R2 = 30k / 4.7k = 6.38. In other words, R1 is 6.38 times greater resistance than R2. My first instinct is:

- that means the voltage at the top of R2, ie. the base bias voltage, will be 10v - 6.38 = 3.62vdc, because R1 will drop 6.38vdc. How would I know, though, that is the correct base bias voltage?

I am very clumsy here with not being able to remember, I apologize if I seem naive, but I think once I get back into it, I will remember more.

I intentionally did not go into the details in order to keep it simple.

1) Calculate the current through R3, e.g. (10V - 5V)/1kΩ = 5mA
2) Ignoring the base-emitter current for now, voltage across R4 = 5mA x 100Ω = 500mV
3) Assume base-emitter voltage = 0.7V, this puts the base voltage at 0.7V + 0.5V = 1.2V
4) Calculate the R1+R2 voltage divider to give 1.2V base bias, e.g. R1 = 34kΩ
5) Fine tune R1 or R2 from optimum DC bias.

P.S. You are not doing the voltage divider calculation correctly.

Vbias = Vcc * R2 /(R1+R2)

 

I intentionally did not go into the details in order to keep it simple.

1) Calculate the current through R3, e.g. (10V - 5V)/1kΩ = 5mA
2) Ignoring the base-emitter current for now, voltage across R4 = 5mA x 100Ω = 500mV
3) Assume base-emitter voltage = 0.7V, this puts the base voltage at 0.7V + 0.5V = 1.2V
4) Calculate the R1+R2 voltage divider to give 1.2V base bias, e.g. R1 = 34kΩ
5) Fine tune R1 or R2 from optimum DC bias.

Perfect, I appreciate your approach. I will get back to the circuit with these points to try resolving the distortion. Thanks to all for your patience. I still remember BBROYGBVGWGSN. My first electronics job was in the US Navy as an electronics tech. Small, 1" long vacuum tubes on circuit boards. The rust is deep but I'm really happy to get back to something I enjoyed.

 

I don't have a circuit-drawing tool but voltage divider bias is well known:

1) R2 from base to ground - current iteration using 1Kohms
2) R1 from Vcc to base - 1Kohms in current iteration of the circuit
3) Rc from Vcc to the collector - 975 ohms in present iteration of the circuit
4) Re from emitter to ground - 800 ohms in present iteration
5) Vcc is 10vdc in the present circuit
6) I've tried with and without a bypass cap .1 uFd across the emitter resistor, and as a blocking cap between the siggen and the base, with absolutely no change to the distorted output signal.

It just seems to me that if the Q point is midway biased at 5vdc, then the 2vpp siggen input should swing cleanly, up and down across the 5vdc Q point, at least that was my expectation.


This is the circuit - the voltage divider bias example below is the standard way, and the one I followed.
I'm using a 2n3904 NPN for the BJT. Keep in mind the current resistor values are just the most recent iteration and I can easily change them. I started with a DC biasing line of reasoning from https://www.petervis.com/GCSE_Desig...Potential_Divider/Potential_Divider_Bias.html - that was my starting point.

The current iteration is just an attempt, and despite all biasing efforts, the same disfigured signal output shows up.
View attachment 305547

Again, how are you connecting your signal generator to the circuit?

If you are connecting it directly to the base of the transistor, then you have NO biasing at all.

If you are using a 0.1 µF coupling capacitor, then it is interacting with an input impedance of roughly 500 Ω (the two 1 kΩ caps in parallel) which is going to result in a cutoff frequency of about 3 kHz, so your signal frequency needs to be well above that.

Let's ignore the signal for now. With R1 and R2 both at 1 kΩ, you have a DC bias on the base of 5 V, which (assuming V_BE = 0.7 V) gives you an emitter current of 4.3 V / 800 Ω = 5.38 mA. Assuming a beta of about 100, that gives you a collector current of about 5.32 mA making the collector voltage 10 V - 5.32 mA)(975 Ω) which is 4.81 V.

This means that your Vce is just 0.52 V and your transistor is on the verge of saturation. It's only going to take a signal voltage of about 100 mV added to the DC bias to drive the transistor into saturation.

Run the numbers.

Let's say that you have a signal voltage of 100 mV added to the bias. That takes your base voltage up to 5.1 V, which takes your emitter voltage to 4.4 V and your emitter current to 5.5 mA. Your collector current is going to be about 5.45 mA which is going to put the collector voltage at 4.69 V, making Vce just 300 mV. If you aren't seeing distortion by this point, you can expect to see it pretty shortly as the signal gets larger.

One of the key factors that you want to aim for is as large a Vce with no signal that you can manage (and consistent with other constraints). The reason is simple -- as your input signal takes the base voltage higher, the additional current in the emitter resistor not only brings the emitter voltage higher, but it results in additional collector current which brings the collector voltage lower. The effect is to pinch off the collector-emitter voltage quickly.

What is it that you are trying to achieve with this amplifier? You aren't getting much gain out of it, perhaps 20%.

 

Again, how are you connecting your signal generator to the circuit?

If you are connecting it directly to the base of the transistor, then you have NO biasing at all.

If you are using a 0.1 µF coupling capacitor, then it is interacting with an input impedance of roughly 500 Ω (the two 1 kΩ caps in parallel) which is going to result in a cutoff frequency of about 3 kHz, so your signal frequency needs to be well above that.

Let's ignore the signal for now. With R1 and R2 both at 1 kΩ, you have a DC bias on the base of 5 V, which (assuming V_BE = 0.7 V) gives you an emitter current of 4.3 V / 800 Ω = 5.38 mA. Assuming a beta of about 100, that gives you a collector current of about 5.32 mA making the collector voltage 10 V - 5.32 mA)(975 Ω) which is 4.81 V.

This means that your Vce is just 0.52 V and your transistor is on the verge of saturation. It's only going to take a signal voltage of about 100 mV added to the DC bias to drive the transistor into saturation.

Run the numbers.

Let's say that you have a signal voltage of 100 mV added to the bias. That takes your base voltage up to 5.1 V, which takes your emitter voltage to 4.4 V and your emitter current to 5.5 mA. Your collector current is going to be about 5.45 mA which is going to put the collector voltage at 4.69 V, making Vce just 300 mV. If you aren't seeing distortion by this point, you can expect to see it pretty shortly as the signal gets larger.

One of the key factors that you want to aim for is as large a Vce with no signal that you can manage (and consistent with other constraints). The reason is simple -- as your input signal takes the base voltage higher, the additional current in the emitter resistor not only brings the emitter voltage higher, but it results in additional collector current which brings the collector voltage lower. The effect is to pinch off the collector-emitter voltage quickly.

What is it that you are trying to achieve with this amplifier? You aren't getting much gain out of it, perhaps 20%.

I was using a 0.1uFd cap to block DC between my siggen and the base of the circuit.
I'm at the end of my day, will read the rest later. I'm semi-retired at age 64 and as you get older, finding means to keep your brain working seems important. Since I have at least SOME memory of this stuff, the mental exercise is like physical exercise you also need at my age. Really important.

The thing about retirement is, the 'novelty' of having nothing productive to do all day wears off fast. There's a chance I might get back into teaching locally. I taught software engineering for 5 years at UC Santa Cruz when we lived in Silicon Valley years ago. There's an opportunity to teach basic electronics locally but it's going to take me a quite while to recall anything. As I discovered with this, my very first attempt, I've forgotten about everything over the decades. It feels like trying to remember 'integration by parts', partial differential equations, and physics from years ago. Not easy.

 

To help refresh your knowledge and skills with this stuff, start off by doing a DC transfer analysis of just your transistors and the collector/emitter resistors.

Assume that an ideal voltage source, Vin, is connected to the base and that the voltage is swept from 0 V to 10 V (your Vcc supply voltage).

First, assume your transistor is absolutely ideal. The beta is infinite and the operates in the linear region right down to Vce = 0 V, at which point it instantly goes into saturation.

Plot the emitter voltage, the emitter current, the collector current, the collector voltage, and the collector-emitter voltage as a function of Vin.

This may sounds like a lot of work, but once you get back on the horse, you will realize that this is almost trivial to do in just a couple of minutes.

 

If you are learning electronics, I suggest downloading the free Spice analog simulation program LTspice from Analog Devices.
I always simulate a circuit first, as it catches most of my mistakes before I build it.
It basically is a virtual lab which you can use to study how electronic circuits work in detail (it's easy to look at the current through or voltage across any component, as well as its power dissipation), or determine how a circuit is likely to work before you build it.
It has a somewhat steep learning curve, but that are good tutorials available for it, and there are several on this website that can help with any questions you have.

 

I am a bit surprised that in no contribution so far the formula for calculating the signal gain has been mentioned.
I think that for a beginner - in addition to the mentioned hints and "rules of thumb" - the formula used almost without exception for practical applications is quite important (common emitter):

A=-gm*Rc/(1+gm*Re)=-Rc/[(1/gm)+Re] .

This formula shows that only for the condition Re>>1/gm (large feedback) the formula reduces to the approximate expression that was mentioned already in this thread: A=-Rc/Re.

The transconductance gm - which is the slope of the voltage control characteristic Ic=f(Vbe) - can be determined directly from the collector DC current: gm=Ic/Vt (with the temperature voltage Vt=26mV for room temperature).

Example 1: A quiescent current of 1mA, will give a value of 1/gm=26 ohms. In this case (and for Re=100 ohms) the simplification Re>>1/gm must not be applied.
Example 2: For a DC current of app. 5.5mA (circuit under discussion with Rc=1k and Re=100) the gain will be A=-1000/(4.5+100)=-9.6. It seems that in this case the approximation with Rc/Re could be exact enough.