Hi, I am playing around with some circuit and I came across something confusing here is the circuit:


So here, I have two registers, initial state they are both storing 0. I input 5 and then R1 stores the 5 and R2 stores 0 which was stored inside R1 previously. Then I input 7 and you see the result from the image above. My question is why is the second register storing the previously stored number from the first register, shouldn't they store the same thing every clock cycle. Why is the current number not going through the second register?Can you explain to me what is happening here?

 

Are the bits being sent in lsb or msb first.

 

Serial ? Parallel ? Edge triggered? or Enable Output or both?

SISO? SIPO? PISO? PIPO?

S= serial, P = Parallel I= input , O= Output

The details are lacking.

What chip are you emulating?

 

Looks parallel to me.

There is a one clock delay between the outputs of the first and second register. On the next clock, the output of the second will be 7.

 

Looks parallel to me.

There is a one clock delay between the outputs of the first and second register. On the next clock, the output of the second will be 7.

I suspect you are correct.

Wouldn't it be nice if people would provide the relevant information? Oh well, that's all part of the learning process.

 

I suspect you are correct.

Wouldn't it be nice if people would provide the relevant information? Oh well, that's all part of the learning process.

On the one hand, to the OP's credit, he did say 'register' and not flip-flop.
On the other hand, I suppose it'd be ok to call a flip-flop a 1 bit register.
But back to the first hand, his bus was clearly labeled as holding 8 bits of data concurrently.
But on the other, his blocks show the standard symbol for a 1 bit D flip-flop.
And, regarding the first hand, his text does indirectly indicate a full 8 bit transfer in one clock.
But, on the other hand, "indirectly"...

 

I am beginner so I don't know about serial parallel or what not, I am using an 8 bit register (that is what it looks like in logisim). You were saying there is a clock delay but how is it delayed exactly when the same clock is attached to both registers.?

Sorry for late reply.

 

I am beginner so I don't know about serial parallel or what not, I am using an 8 bit register (that is what it looks like in logisim). You were saying there is a clock delay but how is it delayed exactly when the same clock is attached to both registers.?

This is a homework problem. Throw away logisim, and try to understand how clocked logic works for yourself.

You can do this with pencil and paper (and a gate level logic diagram of a single bit flip-flop).

 

I am beginner so I don't know about serial parallel or what not, I am using an 8 bit register (that is what it looks like in logisim). You were saying there is a clock delay but how is it delayed exactly when the same clock is attached to both registers.?

Sorry for late reply.

Think of it like a hallway with multiple doors that all open at the same time and stay open just long enough for one person to just step through. So if you are standing before the first door when it opens you are only able to get through that door (and not through the next door) before the doors close. You are now trapped between the doors until they open again, at which point you can get through the next door, but no more. So each time the doors open you are able to advance down the hallway exactly one door's worth. That is how the register delays work. It takes a certain amount of time for the data at the input to appear at the output and by then the clock input of the next register has already been asserted long enough so that it is no longer sensitive to changes at its data input.

 

Okay, that makes sense. I was thinking the inputs are just chilling in the wire in front of the registers and gets in once the clock is high

 

Okay, that makes sense. I was thinking the inputs are just chilling in the wire in front of the registers and gets in once the clock is high

FYI, there is a logic block called a 'latch' the performs the way you had presumed.

 

In sequential logic when the clock edge is sync'd on all registers, it is shifted from one register to the next after successive clock edge loads.
Thus the next registers stores what the input register had just before they all change at the same time.

Details get into terms like setup time, hold time relative to clock. But this is how all serial 1 bit or n-bit wide parallel registers work in Synchronous fashion.