Okay, I'll admit I don't know how useful my adder is. I just found it in some archive and it seemed really useful maybe. My main project right now is in biological engineering and it's called CVAX/CAX.

 

Yeah, we ******* There are xor gates in there.

Can't we use this gate to build bigger 4 bit adders by using it as a base for the first 4 bit adder?

 

Besides, I don't have the money to patent it with the office right now.

Well, now that you've disclosed it publicly you won't be able to get a valid patent in most jurisdictions.

 

Well, now that you've disclosed it publicly you won't be able to get a valid patent in most jurisdictions.

There is such thing as an automatic patent.

 

So you are comparing yours to one that has input and output buffers, when yours doesn’t?

Not sure if this is aimed at me or not.

If you implement this using discrete SSI logic chips, then the prop delay is largely independent of the logic implementation because that is dominated by the I/O circuits. But the notion of commercializing a discrete implementation of a four-bit carry-lookahead adder is pretty preposterous, so the discussion only makes sense in the context of an integrated implementation.

 

Not sure if this is aimed at me or not.

If you implement this using discrete SSI logic chips, then the prop delay is largely independent of the logic implementation because that is dominated by the I/O circuits. But the notion of commercializing a discrete implementation of a four-bit carry-lookahead adder is pretty preposterous, so the discussion only makes sense in the context of an integrated implementation.

No, at the TS (if it were aimed at you it would quote you or start with @WBahn). The TS says that the example in stackexchange has 6 gate delays, but it has an input non-inverting buffer and and output non-inverting buffer, and his has no buffers.

 

Can't we use this gate to build bigger 4 bit adders by using it as a base for the first 4 bit adder?

Not without incorporating carry-in and carry-out logic. The carry-out logic will almost double the size of the design.

 

Okay, I'll admit I don't know how useful my adder is. I just found it in some archive and it seemed really useful maybe. My main project right now is in biological engineering and it's called CVAX/CAX.

Hold on.

You are claiming to own the intellectual properly rights to a design that you found in some archive????

 

There is such thing as an automatic patent.

My understanding of the term "automatic patent" is merely the use of generative AI to produce patent documents.

Are you sure you aren't thinking about automatic copyrights? Very different thing.

 

Hold on.

You are claiming to own the intellectual properly rights to a design that you found in some archive????

That is the way I read it. Sorry, it doesn’t work that way. You either stole it, or it is in the public domain. In either case, you have no more right to it than anyone else. If it is patented, and you try to sell it, you are committing a crime, or at least a tort.

 

Hold on.

You are claiming to own the intellectual properly rights to a design that you found in some archive????

It's MY ARCHIVE!

 

That is the way I read it. Sorry, it doesn’t work that way. You either stole it, or it is in the public domain. In either case, you have no more right to it than anyone else. If it is patented, and you try to sell it, you are committing a crime, or at least a tort.

Or, I designed it myself at the UC of Santa Barbara on a homework assignment. Which, by the way, is what actually happened.

 

College level engineering level homework does sometimes include developing a system to learn the stages of design creation. Developing the proof for a theorem is common in senior level math classes, or at least it used to be common. Back in 1972.

 

It's MY ARCHIVE!

Okay.. Thanks for the additional info.

 

Or, I designed it myself at the UC of Santa Barbara on a homework assignment. Which, by the way, is what actually happened.

Very few (as in, vanishingly few, but not zero) homework assignments are going to yield new things. It's largely baked into the nature of the beast. Good ones lead you to discover and invent things that are new to you, and thus seem revolutionary, but in actuality you have been lead down a path of rediscovering and reinventing things that have been well-known for decades, centuries, or even millennia.

If you look at the Wikipedia page on carry-lookahead adders, you'll find the following circuit.



Notice that this circuit supports both carry-in and carry-out. Also note that the carry-out logic is nearly half of the gates. If we trim out the carry-in and carry-out logic, we get the following simplified version.


I've added letter identifiers to each gate to make it easier to compare it to your schematic.



As you can see, your circuit is identical to the stripped down one, except that yours has redundant 3-input XOR gates (which will add a significant number of transistors to the circuit).

This is really something that you should have done, as the person thinking that you might have something with commercial potential.

On a side note, I certainly hope you have learned to produce much cleaner work-product than this represents. Had you turned this in for grading in one of my classes, it would have received little or no credit. It is in your best interest to present your work in a clear and well-organized manner so that your audience wants to engage with it, whether that audience is your supervisor, your customer, or the grader. I always told my graders (when I had them) that they were not to spend any more time and effort trying to decipher someone's sloppy work than that work represented in terms of effort to make it presentable. If the student didn't care enough about getting a good grade to put in the effort to make it easy to follow, then move on to the work of someone that did.

 

Very few (as in, vanishingly few, but not zero) homework assignments are going to yield new things. It's largely baked into the nature of the beast. Good ones lead you to discover and invent things that are new to you, and thus seem revolutionary, but in actuality you have been lead down a path of rediscovering and reinventing things that have been well-known for decades, centuries, or even millennia.

If you look at the Wikipedia page on carry-lookahead adders, you'll find the following circuit.

View attachment 354224

Notice that this circuit supports both carry-in and carry-out. Also note that the carry-out logic is nearly half of the gates. If we trim out the carry-in and carry-out logic, we get the following simplified version.

View attachment 354228
I've added letter identifiers to each gate to make it easier to compare it to your schematic.

View attachment 354229

As you can see, your circuit is identical to the stripped down one, except that yours has redundant 3-input XOR gates (which will add a significant number of transistors to the circuit).

This is really something that you should have done, as the person thinking that you might have something with commercial potential.

On a side note, I certainly hope you have learned to produce much cleaner work-product than this represents. Had you turned this in for grading in one of my classes, it would have received little or no credit. It is in your best interest to present your work in a clear and well-organized manner so that your audience wants to engage with it, whether that audience is your supervisor, your customer, or the grader. I always told my graders (when I had them) that they were not to spend any more time and effort trying to decipher someone's sloppy work than that work represented in terms of effort to make it presentable. If the student didn't care enough about getting a good grade to put in the effort to make it easy to follow, then move on to the work of someone that did.

Hmmm, reminds me of that time I invented bead-sort and it appeared on Wikipedia right after.

 

Wbahn;
I would like to congratulate you for your restraint and patience with someone with a foul attitude like the TS.

 

Okay, I only see and and or gates in my diagram. I just realized that all of you may just be idiots.

Just in case the TS attempts to edit his post.

 

What kind of engineer are you? Gate delays for gate delays? You obviously have a different definition of gate than us.

In belated answer to your question, I spent most of my career as a full-custom mixed-signal ASIC designer. One of the chips I worked on is currently in orbit about Mars. I also helped develop one of the early low-noise logic libraries for a small company called TSMC so that digital logic on mixed-signal chips didn't inject so much noise into nearby sensitive analog circuits. I've implemented and characterized these libraries on well over a dozen processes from several fabs.

 

The design, as I had learned way back then, should have started with a truth table. That is often the fast way to design logic needing more than a very few gates. And it has the hidden advantage of being self checking.