Can someone double check my K-map equation?

WBahn

Joined Mar 31, 2012
26,398
What is it that you are trying to do? Get the minimal SOP expression, or get one that has no static-1 hazards (i.e., includes all consensus terms)?

Are you allowed to use more than two inputs per gate?

Are you familiar with DeMorgan's Theorem? If so, what happens if you apply it to an OR gate?
 

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SumTingWong

Joined Jan 22, 2015
22
1. I'm honestly not sure what that means, I'm still pretty new to this.

2. Yes

3. Wouldn't that just create more OR gates? or is it possible to apply it to the groups like (W'Y'Z')(W'XY')(XY'Z)(WY')(WX'Y')(W'YZ')?
 

WBahn

Joined Mar 31, 2012
26,398
1. What is the assignment, exactly? That will help us determine what it is you are supposed to be doing. If you don't know about consensus terms, then my guess is that you are looking for the minimal SOP expression which has two fewer terms than you have. You want the fewest number of groups that cover all of the 1's.

2. That makes it very straight-forward.

3. Think about how you implement a straight-up SOP expression. You have a layer of AND gates each of which takes a collection of (possibly inverted) input signals. These outputs of these are all then ORed together, right? DeMorgan's thereom says that you can replace an OR gate with an AND gate provided all of the inputs and outputs are inverted, right? What is an AND gate with an inverted output? As for the inverters on the inputs, is there anything that prevents you from moving each of those from the input of the (former) OR gate to the outputs of the AND gates in the first layer?
 

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SumTingWong

Joined Jan 22, 2015
22
1. What is the assignment, exactly? That will help us determine what it is you are supposed to be doing. If you don't know about consensus terms, then my guess is that you are looking for the minimal SOP expression which has two fewer terms than you have. You want the fewest number of groups that cover all of the 1's.

2. That makes it very straight-forward.

3. Think about how you implement a straight-up SOP expression. You have a layer of AND gates each of which takes a collection of (possibly inverted) input signals. These outputs of these are all then ORed together, right? DeMorgan's thereom says that you can replace an OR gate with an AND gate provided all of the inputs and outputs are inverted, right? What is an AND gate with an inverted output? As for the inverters on the inputs, is there anything that prevents you from moving each of those from the input of the (former) OR gate to the outputs of the AND gates in the first layer?
1. Design a circuit for a 7-segment display which controls the 'c' segment using NAND and NOT gates, it should not light for inputs 10-15
 

WBahn

Joined Mar 31, 2012
26,398
1. Design a circuit for a 7-segment display which controls the 'c' segment using NAND and NOT gates, it should not light for inputs 10-15
Thanks. Is there any general guidance, perhaps just based on the material you are covering right now, that indicates you are expected to some up with the minimal SOP form (or something else)? If not, then let's assume that's the case.

Look at your map and figure out the fewest number of groupings you can use to cover all the 1s. Start with the groupings you have and look at any 1 term that belongs to two or more groups. Is there a way to remove one of those groups and still cover all of the 1 terms in the map? You may need to change groupings a bit to do it. Sometimes it helps to add EVERY possible grouping that exists and then eliminate ones that are redundant.
 

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SumTingWong

Joined Jan 22, 2015
22
Thanks. Is there any general guidance, perhaps just based on the material you are covering right now, that indicates you are expected to some up with the minimal SOP form (or something else)? If not, then let's assume that's the case.

Look at your map and figure out the fewest number of groupings you can use to cover all the 1s. Start with the groupings you have and look at any 1 term that belongs to two or more groups. Is there a way to remove one of those groups and still cover all of the 1 terms in the map? You may need to change groupings a bit to do it. Sometimes it helps to add EVERY possible grouping that exists and then eliminate ones that are redundant.
I'm not even sure what minimal SOP form is. Is that just the most basic expression it could be simplified down to? And I'm not entirely sure about rules of grouping on the kmap. In the first part of our lab all the groups were of 4, in squares and long lines, but in this one theres groups of 2 and 3, other than the top 2/bottom 2 that wrap together? Im guessing i screwed up in the 2nd row and those 3 should be 1 group together, but do i keep the vertical groups going into them?
 

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SumTingWong

Joined Jan 22, 2015
22
I think i put wrong values onto my kmap :/ fixing now

Edit: 2nd column is all 1s and 3rd is all 0s and the first column should be 1010 not 1001
 

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SumTingWong

Joined Jan 22, 2015
22
Ok so i got the equation: W'X + WX'Y' + X'Y'Z' + W'YZ. now i just need to figure out the NAND and NOT part

Im just guessing here but i think for W'X for example i would go W' NAND (X)'? add a not gate to the x and then it would go back to being an x right? I'm still not sure how to entirely get rid of OR gates though
 

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SumTingWong

Joined Jan 22, 2015
22
I tried to make an edit and forgot to submit like an hour ago so I'll try to remember what i asked

Would it be (W'X)' (WX'Y')' (X'Y'Z')' (W'YZ)' after demorgans = (WX') (W'XY) (XYZ) (WY'Z') and then for NAND i think i figured I would just add a not gate before everything that doesnt already have a not? I'm not sure if that makes sense, it's hard to figure out exactly how its going to work without having LogicWorks. I'd like to get this all solved before tomorrow morning though so I can just go to the lab make the circuit up quick then go to class

Edit: Or do I just need to add a NOT gate after each NAND to cancel it out?
 

WBahn

Joined Mar 31, 2012
26,398
I'm not even sure what minimal SOP form is. Is that just the most basic expression it could be simplified down to? And I'm not entirely sure about rules of grouping on the kmap. In the first part of our lab all the groups were of 4, in squares and long lines, but in this one theres groups of 2 and 3, other than the top 2/bottom 2 that wrap together? Im guessing i screwed up in the 2nd row and those 3 should be 1 group together, but do i keep the vertical groups going into them?
The phrase "most basic expression" or "simplest expression" if very ambiguous (even though it gets used -- and abused -- a lot in text books). The SOP form is Sum of Products and it is an expression of the form AB+CD+AD with perhaps some of the variables complemented (inverted). Do you see why it's called SOP. The other one is POS which, as you might guess, is Product of Sums. That would be an expression of the form (A+B)(C+D)(A+D), again with perhaps some of the variables complemented.

You might look at my blog on this: http://forum.allaboutcircuits.com/blog/boolean-logic-sop-and-pos-forms.583/

Your K-map groupings always have to be in integer powers of two, so 1, 2, 4, 8, etc. You can't ever group 3 together.

kmap.jpg

I've identified all of the groupings that there are, namely eight of them. Each one represents an ANDing of three of the (sometimes complemented) variables. The results of those then must be ORed together, so you have a SUM consisting of eight terms, each term consisting of three factors. Make sense?

But some of those terms are redundant and can be left out. Can you see a subset of that groups that are sufficient to make sure that every 1 is included in every group? Sure you can, you've already come up with one of them that uses only six terms. But there are two subsets that you could use that only need four terms. Can you find them?
 

WBahn

Joined Mar 31, 2012
26,398
You are directly tying the outputs of logic gates together. So if one of them is trying to be LO and two of them are trying to be HI, what is the result?
 

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SumTingWong

Joined Jan 22, 2015
22
You are directly tying the outputs of logic gates together. So if one of them is trying to be LO and two of them are trying to be HI, what is the result?
It will come out low? Your talking about the very end points right? How can i get them all to c without connecting?
 

WBahn

Joined Mar 31, 2012
26,398
It will come out low? Your talking about the very end points right? How can i get them all to c without connecting?
Why do you think that it will come out LO? What if I connect 100 outputs together and 99 of them are trying to drive HI and one of them is trying to drive LO? Does it make sense that the one output will be able to overdrive 99 others?

What you have created is a situation known as "contention" where two outputs have the possibility to "fight" and, in general, it's anyone's guess who will win. Very often, the result is an intermediate voltage that is an undefined logic state and, in CMOS circuits, has the very real potential to result in "shoot-through" in which both the pull-up and pull-down transistors are turned on and large current flow between the supply rails, often destroying the chip in very short order.

If you have several outputs and you want one of them to force a LO at regardless of the state of the other outputs, then that is the same as saying that you want a signal that is only HI when ALL of the output signals are HI. Sounds an awful lot like an AND gate, doesn't it?
 

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SumTingWong

Joined Jan 22, 2015
22
Why do you think that it will come out LO? What if I connect 100 outputs together and 99 of them are trying to drive HI and one of them is trying to drive LO? Does it make sense that the one output will be able to overdrive 99 others?

What you have created is a situation known as "contention" where two outputs have the possibility to "fight" and, in general, it's anyone's guess who will win. Very often, the result is an intermediate voltage that is an undefined logic state and, in CMOS circuits, has the very real potential to result in "shoot-through" in which both the pull-up and pull-down transistors are turned on and large current flow between the supply rails, often destroying the chip in very short order.

If you have several outputs and you want one of them to force a LO at regardless of the state of the other outputs, then that is the same as saying that you want a signal that is only HI when ALL of the output signals are HI. Sounds an awful lot like an AND gate, doesn't it?
So i should put a NAND followed by a not at the end?

Edit: or would it be best to undo demorgans and use this http://m.instructables.com/id/OR-gate-from-NAND-gate/ ?
 

WBahn

Joined Mar 31, 2012
26,398
So i should put a NAND followed by a not at the end?

Edit: or would it be best to undo demorgans and use this http://m.instructables.com/id/OR-gate-from-NAND-gate/ ?
It would be best to think through the suggestion I made regarding DeMorgan's and the SOP form. You have one layer of AND gates followed by an OR gate. Apply DeMorgan's to the OR gate and the way to convert that whole thing to NAND gates should become obvious.
 

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SumTingWong

Joined Jan 22, 2015
22
http://imgur.com/a/z4XXS

Updated kmap and equations and 3 circuits i thought may work but didn't. I need to add a NOT to the wx on the first one but otherwise I'm not sure where im going wrong. I'm pretty sure i understand what you're telling me to do
 

WBahn

Joined Mar 31, 2012
26,398
PLEASE post your images HERE and not on some third party site (especially one that always wants to install cookies on my machine).

You have a different K-map. Is this a different problem?

Please show your work step by step. I can't tell where you are going wrong when I can't see where you went at all.
 

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SumTingWong

Joined Jan 22, 2015
22
PLEASE post your images HERE and not on some third party site (especially one that always wants to install cookies on my machine).

You have a different K-map. Is this a different problem?

Please show your work step by step. I can't tell where you are going wrong when I can't see where you went at all.
Sorry, didn't realise. Would you like me to repost them?

I made a comment about halfway up saying i screwed up a couple values, this is the same problem still.

Which part do you want me to show work on? The equation?
I'll be back in the lab in an hour and 45 mins or so if you need me to show something with the circuits but I'll only have like an hour and a half before this is due once i get there.
 
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