my projects is : 8 4 -2 -1 to seven segment using 7400 ic (NAND Gates) only

 

Sounds more like you are saying you need someone to do your uni project for you.

Do you need someone to just give you a schematic or would you prefer one of those picture-like wiring diagrams?

 

Sounds more like you are saying you need someone to do your uni project for you.

Do you need someone to just give you a schematic or would you prefer one of those picture-like wiring diagrams?

i just want the wiring diagram

 

what trips you? create a map of input states and output states. then determine logic that is needed for each output. finally create that logic using NAND gates.

 

already did it; it would take about 10 ICs and more than 100 wires, and I tried the connection. A lot of components got burnt. I just want more ideas or if there is a simpler way to do it. Note that I am a first-year student, so I don't have that much experience in logic design; I am just seeking real help, not attention.

 

so post your circuit and reasoning. we can help identify and correct wrong ideas. this is meant to help people learn from the exp3rience

 

i just want the wiring diagram

The poster was being facetious. This is Homework Help, not Homework Done.

 

it would take about 10 ICs and more than 100 wires, and I tried the connection. A lot of components got burnt.

Do you have access to a logic simulator?

 

Yes, I tried it on Falstad, and it worked perfectly, but due to a lot of wires and connections, it became very complicated when applying it, so I just wanted to knowif there is any way to make the circuit simpler.
these are the boolean functions i reached:

seg_a = NAND(
NAND( NAND(A', B) , NAND(A', B) ),
NAND( NAND( NAND(C, D') , NAND(C', D) ) , NAND( NAND(C, D') , NAND(C', D) ) )
)

seg_b = NAND(
NAND( NAND(A, B') , NAND(A, B') ),
C
)

seg_c = NAND(
NAND( NAND(A', C) , NAND(A', C) ),
D'
)

seg_d = NAND(
NAND( NAND( NAND(B, D') , NAND(C, D') ) , NAND( NAND(B, D') , NAND(C, D') ) ),
NAND(
NAND( NAND( NAND(B, C') , NAND(B, C') ) , D ),
NAND(A, C) )
)
seg_e = NAND( NAND(B, D') , NAND(C, D') )

seg_f = NAND(
NAND( NAND( NAND(B, D') , NAND(C', D') ) , NAND( NAND(B, D') , NAND(C', D') ) ),
NAND( NAND( NAND(A, C) , NAND(A, C) ) , D )
)

seg_g = NAND(
NAND( NAND( NAND(A, D') , NAND(B, C') ) , NAND( NAND(A, D') , NAND(B, C') ) ),
NAND( NAND( NAND(A, C) , NAND(C, D') ) , NAND( NAND(A, C) , NAND(C, D') ) )
)

 

my projects is : 8 4 -2 -1 to seven segment using 7400 ic (NAND Gates) only

What is the meaning of "8 4 -2 -1"? does it indicate 4 bit binary with powers of 2? if so why the - sign on the 2 and 1?

 

What is the meaning of "8 4 -2 -1"? does it indicate 4 bit binary with powers of 2? if so why the - sign on the 2 and 1?

Indicates the decimal value of the 4 inputs
A=8
B=4
C=-2
D=-1

 

 

What should the 7-segment display for an input of 0011?
What should it display for 1100?

There's no way to solve a problem unless the problem is clearly understood.

 

What should the 7-segment display for an input of 0011?
What should it display for 1100?

There's no way to solve a problem unless the problem is clearly understood.

For the undesired outputs a led will indicate that the output is out of range 0-9

 

Hello,

How would the error look like?
Or could you display blanks when out of range?

Bertus

 

Hello,

How would the error look like?
Or could you display blanks when out of range?

Bertus

Blanking, or having '-' would be reasonable in a real world situation. But he said that there is a separate LED that will indicate this. So, presumably, the 7-seg display output can be treated as don't cares for the six invalid input patterns. Of course, that's a guess on my part. As is so often the case, we are being asked to help with something but only given dribs and drabs of the relevant information as we drag it out of the TS.

I still can't figure out just what the TS is asking us to help with. He says that he has a solution that works perfectly in the simulator, but then burns up chips when he wires it up. That would indicate that he didn't wire it up according to his logic design, or that his logic design is one that works in simulation by not in the real world because of issues like floating inputs. I don't know how we can be expected to help with that since he has given NO clue (other than that it involved 10 ICs and 100 wires) as to how he wired it up. Not even whether he is using TTL or CMOS or what ever other logic family. We don't know how much current each of these segments needs. Whether he is driving them directly from logic gate outputs and, if so, whether they are capable of driving them. We don't know if his 7-seg display is common-anode or common-cathode. We don't know any of these things, yet we are expected to tell him what is wrong or how to do it differently.

 

1100 using those values would be 1*(8)+1*(4)+0*(-2)+0*(-1)=12
0011 would be 0*(8)+0*(4)+1*(-2)+1*(-1)=-3

 

Not even whether he is using TTL or CMOS or what ever other logic family.

That was specified in the first post and again in the confusing post #12 where negative numbers were specified.

using 7400 ic (NAND Gates)

 

That was specified in the first post and again in the confusing post #12 where negative numbers were specified.

I tend to not infer that 7400 means TTL, since unadorned 74xx part numbers are often used as family-agnostic references to to logic functions. But, lacking further information, we can run under the assumption that he is using 5 V TTL logic gates.

Of course, this assumption makes some of the other unknowns even more important. The 7400 can only source about 400 µA of current and the output when doing so may be as low as 2.4 V. This is particularly relevant if his display is common-cathode.

 

1100 using those values would be 1*(8)+1*(4)+0*(-2)+0*(-1)=12
0011 would be 0*(8)+0*(4)+1*(-2)+1*(-1)=-3

Yes, and hence the query about one a one-digit 7-seg display should display for those inputs.

The TS has indicated that there is a separate LED that will illuminate when the input pattern does not represent a valid decimal digit value. Though this begs the question of whether the TS is also supposed to implement the logic for the LED.