Can I use HSYNC and VSYNC to make DE using MachXO2?

Thread Starter

tyro01

Joined May 20, 2021
24
Can I use HSYNC and VSYNC to make DE(Data Enable) using Lattice XO2-1200HC with PLL?
The expected input VGA format is 640*480 60/75Hz.
I don't have any knowledge of VHDL, but would like to know if it is technically possible.
 

Deleted member 115935

Joined Dec 31, 1969
0
what do you mean by a "data enable" ? Yes it "enables the data" , but when ?

can you draw a timing diagram of what you want relative to the Hsync / vsync please.

Is this the RGB receiver circuit ?
is this RGB form a digital source or an analog one ?
i askas the digital ones tend to be much wider band , sharper edges than analog ones.


The MaxX02 is just a very old , simple digital FPGA , with a very "quaint" user front end
if you want to do some logic design in main stream, you would be better looking at main stream products such as the Xilinx or Intel/ Altera ranges.
 

Thread Starter

tyro01

Joined May 20, 2021
24
DE indicates an effective pixel. My idea is to use a 31.468kHz HSYNC and make a 25.175MHz PIXCLK with a PLL. The specific values for the horizontal back porch and horizontal front porch are given in the LCD datasheet, so I will make a gate signal that excludes those periods. My concern is whether the PLLs in MachXO2 will be able to handle my usage. I am not familiar with the history of FPGAs, so I did not know that MachXO2 is old.pict.jpg
 

Thread Starter

tyro01

Joined May 20, 2021
24
The Lattice website states that the XO2-1200 has a PLL unit.
list.jpg

However, I seem to have misunderstood the use of the PLL built into the FPGA. I am searching for all products from Analog Devices. I am currently working on the specifications for the ADV7401. This device seems to be able to output a DE signal.
 

Deleted member 115935

Joined Dec 31, 1969
0
Yes, you are right, the FPGA contains a PLL, and it CAN be used for some real interesting circuits
but its main aim, and how its designed to be use, is internal clock,
it needs a clock in against which its comparator can compare against,
your design needs to synchronise to a very occasional edge.

Sorry, I condensed all that down to " thats not what the PLL in the fpga you quote are designed to do "
 
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