CAN bus ack related doubt

Discussion in 'Embedded Systems and Microcontrollers' started by ep.hobbyiest, Jul 28, 2015.

  1. ep.hobbyiest

    Thread Starter Member

    Aug 26, 2014
    i have one doubt in CAN bus ack.
    When Node A sends data to Node B that time node B gives acknowledge to node A. But this ack in which form. It is also one kinda frame or something different?
  2. JohnInTX


    Jun 26, 2012
    The ACK is not a separate reply message. After NodeA sends the CRC at the end of the data in a message, it sets the bus to 'recessive' i.e. does not drive the bus. This is the ACK slot. If NodeB (or any number of nodes) has received and accepted the message, it sets the bus to 'dominant' i.e. goes active for one bit time which is interpreted by NodeA (the sender) as an ACK. If no nodes receive / accept the message, this bit will remain recessive (not driven) for the ACK bit slot. The master detects this and knows that the message did not get through to any slaves.

    Its similar to how I2C generates an ACK; the sender sends data then floats the bus and generates a clock to see if any slave pulls the bus low for that one bit (the ACK).

    AN713 from Microchip describes this and other stuff. The CAN spec from BOSCH goes into even more detail..
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  3. Papabravo


    Feb 24, 2006
    The ACK is in the form of a single dominant bit in the ACK slot. The transmitter outputs a recessive level on the bus during this bit. Every receiver on the bus that successfully reads the message will set the bus level to dominant during the ACK slot. Any receiver that detects an ERROR during the transmission will throw an ERROR Frame (Active or Passive) to abort the frame before it ever gets to checking the CRC. A transmitting node that sees a recessive level during the ACK slot will assume it is lonely and retry the entire frame -- forever, if it remains lonely.
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