Hi
As far we know, a 2-input NAND gate has 4 possible states. Now I want to calculate PDP of my gate. Here, I don`t know how I find my delay. Means for which state Should I calculate delay? Or, maybe I should calculate the four delay for four states and choose the longest one?

Thanks.

 

Is this gate in a chip or is it made by you from discrete components?

 

Hi
As far we know, a 2-input NAND gate has 4 possible states. Now I want to calculate PDP of my gate. Here, I don`t know how I find my delay. Means for which state Should I calculate delay? Or, maybe I should calculate the four delay for four states and choose the longest one?

Thanks.

In general, you calculate all of the possible delays and use the longest one. That's when you need a single delay number. Sometimes you give different delays for specific transitions or, more commonly, for the delay coming from different inputs to different outputs (in the case of a more complicated gate, such as a adder).

You actually have more than four delays to calculate (at least in theory). For each input you have a delay when that output goes from LO to HI while the other input is LO and from HI to LO while the other input is LO. Then you have the same two transitions when the other input is HI. That's four delays for just one input. So you have a total of eight delays. However, you can eliminate those for which the output does change, which trims it back quite a bit. The point being that you don't have one delay for each input state.

 

In general, you calculate all of the possible delays and use the longest one. That's when you need a single delay number. Sometimes you give different delays for specific transitions or, more commonly, for the delay coming from different inputs to different outputs (in the case of a more complicated gate, such as a adder).

You actually have more than four delays to calculate (at least in theory). For each input you have a delay when that output goes from LO to HI while the other input is LO and from HI to LO while the other input is LO. Then you have the same two transitions when the other input is HI. That's four delays for just one input. So you have a total of eight delays. However, you can eliminate those for which the output does change, which trims it back quite a bit. The point being that you don't have one delay for each input state.

In fact you are right. but as my both inputs are alike, so 4 of these 8 delays are identical. My problem was that for each delay, should I calculate PDP or choosing the longest delay to calculate PDP for the NAND gate, that I find my answer. Thanks alot.

 

In fact you are right. but as my both inputs are alike, so 4 of these 8 delays are identical. My problem was that for each delay, should I calculate PDP or choosing the longest delay to calculate PDP for the NAND gate, that I find my answer. Thanks alot.

Ah... but ARE they alike?

If you look at the internal structure of a NAND gate, you will see that you have two NFETs in series. The capacitive load seen by one is not the same as seen by the other, so the delays are slightly different. Most libraries don't try to balance them, because the hassle isn't worth it in most instances.

Of course, I'm assuming we are talking CMOS. But the basic issue is the same with any technology -- inputs that are logically equivalent are seldom electrically equivalent.