CMOS Full adder calculation propagation delay

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Joined Apr 28, 2011
Design A Full-Adder using:
a) CMOS AOI Logic
b) Transmission Gates
c) Dynamic Logic
Choose an appropriate value for the load capacitor say 0.2pF.​
Calculate (analytically) the TPHL and TPLH for part "a"
• Calculate (analytically) the VOL, VOH, VIL, VIH, NML and NML for case "a"​


State assumptions:

Parameters for spice simulation
.model MbreakND NMOS
+ Level=1 Gamma= 0 Xj=0
+ Tox=1200n Phi=.6 Rs=0 Kp=111u Vto=2.0 Lambda=0.01
+ Rd=0 Cbd=2.0p Cbs=2.0p Pb=.8 Cgso=0.1p
+ Cgdo=0.1p Is=16.64p N=1 W=60u L=10u

.model MbreakPD PMOS
+ Level=1 Gamma= 0 Xj=0
+ Tox=1200n Phi=.6 Rs=0 Kp=55u Vto=-1.5 Lambda=0.04
+ Rd=0 Cbd=4.0p Cbs=4.0p Pb=.8 Cgso=0.2p
+ Cgdo=0.2p Is=16.64p N=1 W=30u L=10u



Joined Nov 25, 2009
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