Capacitor calculation to delay high signal

Thread Starter

dxoverdy

Joined Sep 20, 2022
2
Hi there,
I am doing a project on an ESP8266 (Wemos D1 mini) and the digital output pins (3.3v, 12mA) go high during boot phase for around 100ms. The problem is I'd like to use these pins to drive three relays which switches onward processes - however the onward process only needs a brief connection on the relays to do the onward processes.

The problem is, as said, whilst the pins are normally low, they go high during boot up which would ultimately trigger my project - in this case, a garage door, to open, or close, or end up somewhere I don't want it to be. I was thinking of ways to overcome, perhaps by introducing a resistor and capacitor which would absorb 200ms or so of output so it wouldn't trigger on boot, however would work (albeit it with a small delay - not a problem) during normal use as I would just hold the pin high for a longer period.

Can anyone help me with the formula to derive a capacitor and accommodating resistor size (if needed), if this is a suitable solution?
Thanks

* Other solutions very much welcome.

Dan
 

MisterBill2

Joined Jan 23, 2018
13,128
The common method of inhibiting the random output activity during processor startup times is to delay the output enable function until the startup sequence is completed.
Given that I am not at all familiar with the processor you are using, my suggestion is to examine the various control functions to see if there is already an output enable function available. That could be the simplest and most reliable method.
An alternative could be to delay the availability of power to the output devices.
 

Jerry-Hat-Trick

Joined Aug 31, 2022
162
I think your method is possible although I also think MisterBill2's solution is more elegant

I was surprised to find that you can buy 3.3V relays with 16.7mA coil current, but I'm guessing you will be using something a bit meatier? For example, a 12V automotive relay which might need 150mA coil current to switch garage door motors?

If so, I'd connect one side of the coil to the 12V rail, the other to the collector of an NPN transistor with the emitter connected to ground. With a current gain of say 150 you'd need 1.0mA into the base, call it 2.0mA to be sure the transistor is turned hard on. With 0.6V base to emitter drop and 3.3V digital output you need a resistor from the processor to the base which can drop 2.7V so a resistor value of (2.7/2.0)K should be fine. Let's say 1K2.

Then it gets a bit trickier. This is where the engineer saves the world whilst physicists and mathematicians argue about e^(-t/RC) and reach for their calculators. Initially the capacitor is seen as a short to ground and for practical purposes the base to ground resistance is large so the current through the resistor is 3.3/1.2 mA. When the voltage across the capacitor reaches 0.6V the current through the resistor is 2.7/1.2 mA. Near the beginning of the exponential curve it's okay to average this to 3.0/1.2 mA.

C = Q/V = current times time divided by 0.6. This gives a value of C = 3.0/1.2 x 100/0.6 uF = 417uF. Someone please check my maths, especially order of magnitude! This is quite a high value, although a 5V capacitor should be phsically quite small. If you use a darlington pair transistor with a high gain you get a much lower capacitor value because you can maybe use a 10K resistor or higher, and the capacitor need to charge to at least 1.2V before the transistor turns on.
 

MisterBill2

Joined Jan 23, 2018
13,128
When the slowly rising coil current very gently closes and then opens the contacts there will probably be a fair amount of arcing.
In addition that same circuit will delay the relay operation every time, both opening and closing.
Another scheme will be to use a power driver IC with it's own enable input. That would also allow driving bigger relays directly.
 

Thread Starter

dxoverdy

Joined Sep 20, 2022
2
The chip doesn't have a delay output enable unfortunately, I've done plenty of reading of datasheets and it's just the behaviour. There are two pins which are high impedence and don't switch at boot, however they are also clock/data for an OLED screen I've got attached... And I need three relay switches anyway.

The garage door motor has its own control box - the box exposes three pins which when given 12V, one corresponds to up, one to down and one to stop. So the driving from my circuit is minimal, just a few 3.3v relays suitable for the 3.3v logic of the chip.

I then started thinking, well, all three pins (call them D3, D4 and D5) all go high at boot, so maybe a logic IC which can cover off the following truth table?

D1 D2 D3 Out
0 0 0 0
0 0 1 1
0 1 0 1
1 0 0 1
1 1 0 0
1 0 1 0
0 1 1 0
1 1 1 0

The output could be AND with the individual pins prior to the relay so that if proven only one switch is high at any one time, the signal is allowed through?

I thought my luck was in when I saw there was a triple input XOR however 1 1 1 yields 1 as an output. Not that I can think of an elegant set of logic gates which would fulfil the above... yet!

Is this a sensible alternate approach?

Thanks
 

Jerry-Hat-Trick

Joined Aug 31, 2022
162
I'm thinking, maybe you don't need relays, just a few transistors if the control box is happy with a lowish current 12V inputs? Maybe it's okay just to delay the turning on of that 12V supply rail you need for the control box inputs with another I/O line with the delay mechanism I described to turn that supply on? Then the supply can be actively turned on by driving that pin high once the three control lines have been given time to go low, or better driven low. There will be a small voltage drop across the supply rail transistor switch and another across the individual control line transistors but I expect the control box will tolerate this - so long as they aren't actually taking the current that drives the motor.
 

Ian0

Joined Aug 7, 2020
6,294
Just a thought: you say that the pins go high. Are they driven high, or do they go high just because they are inputs with pull-ups?

If the latter, then the pull-ups wouldn’t be able to source enough current to drive an NPN transistor, so problem solved.
 

eetech00

Joined Jun 8, 2013
3,418
The chip doesn't have a delay output enable unfortunately, I've done plenty of reading of datasheets and it's just the behaviour. There are two pins which are high impedence and don't switch at boot, however they are also clock/data for an OLED screen I've got attached... And I need three relay switches anyway.

The garage door motor has its own control box - the box exposes three pins which when given 12V, one corresponds to up, one to down and one to stop. So the driving from my circuit is minimal, just a few 3.3v relays suitable for the 3.3v logic of the chip.

I then started thinking, well, all three pins (call them D3, D4 and D5) all go high at boot, so maybe a logic IC which can cover off the following truth table?

D1 D2 D3 Out
0 0 0 0
0 0 1 1
0 1 0 1
1 0 0 1
1 1 0 0
1 0 1 0
0 1 1 0
1 1 1 0

The output could be AND with the individual pins prior to the relay so that if proven only one switch is high at any one time, the signal is allowed through?

I thought my luck was in when I saw there was a triple input XOR however 1 1 1 yields 1 as an output. Not that I can think of an elegant set of logic gates which would fulfil the above... yet!

Is this a sensible alternate approach?

Thanks
How about disabling any internal pullups for the output pins?
 

MisterBill2

Joined Jan 23, 2018
13,128
The chip doesn't have a delay output enable unfortunately, I've done plenty of reading of datasheets and it's just the behaviour. There are two pins which are high impedence and don't switch at boot, however they are also clock/data for an OLED screen I've got attached... And I need three relay switches anyway.

The garage door motor has its own control box - the box exposes three pins which when given 12V, one corresponds to up, one to down and one to stop. So the driving from my circuit is minimal, just a few 3.3v relays suitable for the 3.3v logic of the chip.

I then started thinking, well, all three pins (call them D3, D4 and D5) all go high at boot, so maybe a logic IC which can cover off the following truth table?

D1 D2 D3 Out
0 0 0 0
0 0 1 1
0 1 0 1
1 0 0 1
1 1 0 0
1 0 1 0
0 1 1 0
1 1 1 0

The output could be AND with the individual pins prior to the relay so that if proven only one switch is high at any one time, the signal is allowed through?

I thought my luck was in when I saw there was a triple input XOR however 1 1 1 yields 1 as an output. Not that I can think of an elegant set of logic gates which would fulfil the above... yet!

Is this a sensible alternate approach?

Thanks
I was not thinking about a DELAY output enable, just an output enable of any sort..
BUT if there is none, then another simple option is to use those relays, but tie the common coil return connections together and to the collector of an NPN transistor , with the emitter tied to the power common side. Then none of the relays can operate until the transistor is biased on. That can be done with a simple RC delay for several seconds after the processor module is switched on, the time delay needing to be longer than the boot-up time but shorter than the time before any intended outputs would be active.
The total additional parts will be one transistor, one resistor, and one capacitor. So it would be rather simple.
 

BobTPH

Joined Jun 5, 2013
5,762
I have used an ESP8266 module myself. They come pre-programmed with wifi tcp/ip software. I suspect the user does not have the means or desire to reprogram it, so solutions that involve that are likely out.
 
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