Hi

I got an assignment from school where I have to build a JK-FF flipflop using only NAND gates with 2 inputs. The transition tables have already been filled out but I can't by the life of me figure out how to build this with NAND gates. Can anyone help me with this? I posted the flipflop design and the transition table below.

The conditions for the flipflop (instead of a horizontal bar for NOT I'm using an ') are:
J1=Q0'
D0=Q1'
K1=Q1&Q0' + Q1'&Q0

 

Forget about the restriction of using NAND gates for now. Implement it using whatever basic logic gates you can. Once you have that, you can worry about replacing each of the gates that is not a 2-input NAND with an equivalent subcircuit that is.

 

You verbal description doesn't seem to mesh with your figure. Are you SURE you are being asked to take a pile of 2-input NAND gates and use them to build up a single JKFF?

The diagram and the equations you gave look like you are given a circuit that already has a JKFF and a DFF in it and you are being asked to use 2-input NAND gates to implement the necessary transfer (i.e., excitation) logic to implement the state machine described in the table.

 

Hey WBahn, thanks for your replies.

I need to use 2NAND's to mimick the output of the transition table. I'm not sure if I understand what you mean. Just a JK flipflop from NAND gates could be something like this: http://upload.wikimedia.org/wikipedia/commons/f/ff/JK-FlipFlop_(4-NAND).PNG

 

Okay, I think I understand what you are being asked to do (which is NOT "to build a JK-FF flipflop using only NAND gates with 2 inputs").

But your transition table needs work because it is not correct. Look at what state you go to the first time you are in State (00) (i.e., Q1=0, Q0=0) and then look what state you say you go to the second time you are in that state. Does that make sense?

Assuming that your excitation equations are correct, can you implement them using OR, AND, and NOT?

 

Hello metiz
So you already got the solution from wikimedia.org.

 

Okay, I think I understand what you are being asked to do (which is NOT "to build a JK-FF flipflop using only NAND gates with 2 inputs").

But your transition table needs work because it is not correct. Look at what state you go to the first time you are in State (00) (i.e., Q1=0, Q0=0) and then look what state you say you go to the second time you are in that state. Does that make sense?

Assuming that your excitation equations are correct, can you implement them using OR, AND, and NOT?

Ah yes I see the error. The last Q1 Q0 needs to be 1 1 (and the bottom line of JKD can be ignored)

I can't use anything else than 2NAND's. All those switches can be made with NAND's though. (a pain in the ass, sure, but...)

 

Hello metiz
So you already got the solution from wikimedia.org.

I got a single JK flipflop from wiki, yes, but that's not the solution to this question, at all.

 

Ah yes I see the error. The last Q1 Q0 needs to be 1 1 (and the bottom line of JKD can be ignored)

That's what I was suspecting. So, to confirm, State 01 is an unused state with undefined behavior, correct?

I can't use anything else than 2NAND's. All those switches can be made with NAND's though. (a pain in the ass, sure, but...)

So at this point I'm not sure what else you are needing assistance with. You can implement all three equations using six 2-input NAND gates. Do you see how to do the J and D logic with just one NAND gate each?

 

Hello metiz

What I try to say in my post #6 is:
If you find out there the related to the JK Flip-Flop’s, well, You can find also the related to the type D Flip-Flop and complement both to form your counter of 2 BIT's.

 

Hey guys,

Thanks for the help so far. I'll double-check the state-table to see if it is correct and if the state 01 is indeed unused, but that'll have to wait untill tomorrow. I have to study for an exam.

 

Ok well as far as I can tell the table looks ok. I've made a simulation with logic simulatot, the top part is an ff flipflop and the bottom part a D. I can only get the bottom 2 lights to light up when I hit the switches

 

Do you mean the bottom two lights of each circuit or the bottom two lights of the entire diagram (u.e., the D flip flop circuit)

(Oh, and did you mean JK flip flop when you said ff flip flop?) The top circuit is not a JK flip flop. There are a few errors in the circuit. First, the NAND gate equivalent of a JK flip flop uses three input NAND gates (which can be built with dual input NAND gates. Second, I think this is a simple error, but you have an AND gate specified instead of a NAND gate. Third, you are missing the connections to that third input (which makes sense, since you didn't have one to connect to).

And to be clear, based on your title, your are talking about several dual input NAND gates being used to make a JK flip flop?

 

Alright this is starting to get messy. The table posted in my first post is ok, up until the 2nd time 0 0 appears. 0 0 = reset so it has 3 defined settings and 1 undefined setting (0 1). Below is the fixed table.

djsfantasi mentioned a bunch of things wrong with my simulated design, for one that there are a bunch of AND gates in there (and an inverter, but that can be replaced with a NAND).

I can't seem to make a JK flipflop. I did rebuilt the D flipflop

@djsfantasi Yes I can only use 2-imput NAND's. I used an inverter above to keep things a bit clearer.

 

Review your simulated circuit against the schematic you posted in post #4. See any differences?

 

Review your simulated circuit against the schematic you posted in post #4. See any differences?

Yeah a lot, no more AND gates for example. This is just a D flipflop, the ther post was (an attempt at) the total system

 

djsfantasi was talking about the post you made for the JK FF in Post #4 that consisted of two 2-input NAND gates and two 3-input NAND gates. Compare that to the top portion of your schematic in Post #12. Do you see the differences?

Does your simulator have 3-input NAND gates? If so, build the JF FF exactly as shown in Post #4 and verify that it works. Then replace the 3-input NAND gates with an appropriate subcircuit of 2-input NAND gates.

When you post your diagram, annotate the inputs and outputs (use Paint if you have to, doesn't have to be fancy) along with any other useful notations, such as the FF type and perhaps even draw a box around the subcircuit that makes up each FF.

 

A crap yes I see. I thought the "3rd" input in the picture in post 4 was just an indication and not an actual input. I can use however many input NAND's as I like. I'll build it again tomorrow. If anyone's interested, I use the "Logic.ly" demo, available as a flash thingy here http://logic.ly/demo/

 

A crap yes I see. I thought the "3rd" input in the picture in post 4 was just an indication and not an actual input.

I think he's got it!

 

I think he's got it!

Yeah...

yet nothing changes. White means 0, blue mean 1 and red means undefined