Hi, I came up with a battery over-discharge protection circuit that I would like some feedback on. The sine wave at the inverting terminals represents a changing battery voltage. The voltages at the non-inverting terminals were chosen for this experiment: When the voltage at the inverting terminals drops below 3V, the output turns off. After the battery has been charged to at least 4.5V, the output turns on.



Here is the Circuit Simulator Applet (falstad.com) code if you want to simulate the circuit. I built it on the breadboard and it works.

$ 13 0.000005 173.42552219524063 43 5 50 5e-11
151 464 256 528 256 0 2 5 5
w 464 272 416 272 0
w 464 336 416 336 0
w 464 240 432 240 0
w 528 256 576 256 0
w 528 352 576 352 0
w 416 272 576 352 0
w 416 336 576 256 0
151 464 352 528 352 0 2 0 5
401 160 128 256 128 1 8\s15\s-15\s1000000\s3\s1.2395309375881978\s100000 0\s20\s10000000000 1\s0
401 160 368 272 368 1 8\s15\s-15\s1000000\s4.5\s1.2395309375881978\s100000 0\s20\s10000000000 1\s0
R 80 16 0 16 0 0 1 4 0 0 0.5
R 160 240 240 240 0 1 0.4 2.5 2.5 0 0.5
w 160 352 160 240 0
162 576 256 656 256 2 default-led 1 0 0 0.01
162 576 352 656 352 2 default-led 1 0 0 0.01
I 304 128 432 128 0 0.5 5
x 518 416 568 419 4 24 OUT
w 576 352 576 400 0
w 432 128 432 240 0
w 656 256 656 352 0
w 656 352 656 416 0
w 160 112 128 112 0
w 128 112 128 240 0
w 128 240 160 240 0
w 160 416 160 384 0
r 256 128 256 64 0 100000
r 320 368 320 304 0 100000
w 256 64 256 16 0
w 272 16 288 16 0
w 256 128 304 128 0
w 320 16 320 304 0
w 272 368 288 368 0
w 288 16 320 16 0
w 288 368 320 368 0
w 320 368 464 368 0
w 272 16 256 16 0
g 656 416 656 448 0 0
x 145 72 218 75 4 24 LM393
x 200 435 273 438 4 24 LM393
x 455 198 609 201 4 24 2x\sCD74HC02
x 345 87 433 90 4 24 CD4069
R 160 144 0 144 0 0 40 3 0 0 0.5
R 160 416 0 416 0 0 40 4.5 0 0 0.5
w 80 16 256 16 0
o 4 64 0 4099 10 102.4 0 2 4 3
o 12 32 0 4099 4.658261269263278 0.0001 1 2 12 3
o 14 32 0 4099 10 102.4 2 2 14 3

 

Does it work well?

 

Does it work well?

Yes it appears to function predictably. After some analysis, the design is similar to a 555 timer. I'm sure there are other ways to go about it though open collector of the LM393 gave me some issues. At least with this configuration of an active LOW SR latch, the control inputs of the NAND gates are never LOW at the same time and so invalid conditions and oscillations are avoided. Improvements would be CMOS comparators and consolidating the 4069 and CD74HC02 chips into a single quad NAND ic.

 

open collector of the LM393 gave me some issues.

What issues.

Below is the LTspice simulation of my take on the circuit, using just one LM393 dual comparator:
The open collector output of U2 shorts R3 to ground when the output is high to generate a change in the threshold for U1's negative input and provide the desired hysteresis.
Notice that U1's output goes low at 3V and high at 4.5V input.

The Ref input at U2 is just to provide a positive voltage of a few volts for proper triggering of U2 form U1's output.

 

Here is an improvement with a 1.2V voltage reference.

 

I am using these parts. Can come in Open Collector.... lol..... Open Drain out put. There are several parts like this on the same data sheet. The RS ff in nice and the reference saves parts.

 

What issues.

Originally I tried an active HIGH SR latch with NOR gates. In light of my latest design I'm reasonably confident the error was purely human. I'll be sure to study the circuit you presented.

I am using these parts. Can come in Open Collector.... lol..... Open Drain out put. There are several parts like this on the same data sheet. The RS ff in nice and the reference saves parts.
View attachment 266720

I didn't think there was anything special about my latch design. Its cool to see its being used for this application.