I'm using a bare-bones Pierce oscillator with a 153.6 kHz crystal for a piece of custom instrumentation using a CD4049UBE hex inverting buffer. The crystal output is sent into two sequential stages of buffer on the same IC to deliver nominally square-wave output. The frequency is dead-on according to the frequency counter, but the square wave isn't symmetric. The "duty cycle" shows the output "low" for about 55% of the time and "high" only about 45%. Is there a way to adjust a circuit like this to get a symmetric output?

 

Please post a circuit.
That makes it much easier to help.
Just a thought, and I do not know if it will work, but can you feed a variable voltage into the oscillator input pin via a resistor, maybe 100K, to tweek the bias? Would that change it?
Otherwise, use a double frequency and divide by 2.

 

See

 

The cd4049-g1 thru -g3 refer to the gates on the hex inverter.

 

I'd go for the 307.2kHz crystal and a divide by two circuit.
But does the duty cycle actually matter?

 

Like almost all schematics posted on these forums the important supply voltage is not shown.
The CD4049 does not have the same output high current and output low current that are used to charge and discharge stray capacitances. Its max output high current is less than half its max output low current.
Use an ordinary CD4069 hex inverter or a 74HC04 (max recommended supply is 6V) to fix the poor symmetry of the waveform.

 

I was assuming that he chose the 4049 because his supply voltage was >5V.
If not then the 74HCU04 would be a better choice. It theoretically should be the unbuffered HCU for the oscillator, not a HC, but I've managed to make Pierce oscillators out of all sorts of buffered gates, NANDs, NORs, EXORs.

 

I'd go for the 307.2kHz crystal and a divide by two circuit.
But does the duty cycle actually matter?

The actual frequency isn't so critical; I was just aiming for something around 150 kHz at the moment. We may want to go as high as 500 kHz. In any case, using a higher-frequency crystal and then putting the output into a flip-flop solved the symmetry issue. The square wave is sent off to a few different places in the circuit, with one portion LP filtered to give something that looks approximately sinusoidal. Having symmetry in the initial square-wave helps make a better approximation to a sinusoid.

 

True - got to be symmetrical to make a good sinewave.
There's a neat circuit with a 4018 and five resistors that makes a pretty good job of a sinusoid from a frequency 10x the required frequency of the sinusoid. It may take me some time to find it .. . .
Or an elliptic filter so that the notch takes care of the 3rd harmonic and the roll-off takes care of the higher harmonics.

 

My sinewave generator uses Don Lancaster's "Opamp or Cmos Cookbook" idea of using a CD4018 counter and 5 resistors to make a "digital" sinewave with steps, then I filter it with a digital switched-capacitor Butterworth lowpass filter IC that uses the same clock as the CD5018. The distortion is almost unmeasurable and the level is flat for a wide range of frequencies.

 

My sinewave generator uses Don Lancaster's "Opamp or Cmos Cookbook" idea of using a CD4018 counter and 5 resistors to make a "digital" sinewave with steps, then I filter it with a digital switched-capacitor Butterworth lowpass filter IC that uses the same clock as the CD5018. The distortion is almost unmeasurable and the level is flat for a wide range of frequencies.

That's the one - you saved me the bother of looking for it! I've also seen a much more mathematical treatment of it that optimises the resistance values for different numbers of stages of Johnson counter. I probably can't find that either.

 

I was assuming that he chose the 4049 because his supply voltage was >5V.
If not then the 74HCU04 would be a better choice. It theoretically should be the unbuffered HCU for the oscillator, not a HC, but I've managed to make Pierce oscillators out of all sorts of buffered gates, NANDs, NORs, EXORs.

Thanks for pointing out the difference beween the HCU vs HC. While I have this working now, I'll order those ICs and make the switch in a few days.

 

My sinewave generator uses Don Lancaster's "Opamp or Cmos Cookbook" idea of using a CD4018 counter and 5 resistors to make a "digital" sinewave with steps, then I filter it with a digital switched-capacitor Butterworth lowpass filter IC that uses the same clock as the CD5018. The distortion is almost unmeasurable and the level is flat for a wide range of frequencies.

This sounds like a great approach. I just ordered the Lancaster books, but I'm also putting together an order from Digikey. Is there a part number for the switched Butterworth LPF?

 

I used a National Semi LMxxx (obsolete now) switched capacitor Butterworth lowpass filter IC but Maxim has some today.

 

@Audioguru again 's filter was a switched capacitor variety, so that its cutoff frequency tracked the oscillator frequency.
If you have a fixed frequency, a MFB filter (or Sallen & Key) made from a single op-amp will do. High-frequency breakthrough is better on the MFB than the Sallen & Key. You could even use a LC filter but the effects of self-resonant frequency on the inductor are much the same as HF breakthrough due to the op-amp's own HF phase shift.

 

I discovered that Don Lancaster has the CMOS Cookbook as a free download on his website just a bit too late. Anyway, I found the explanation for this circuit on pages 379-385. Download from Lancaster's site here:

https://www.tinaja.com/ebooks/cmoscb.pdf

This is probably EE 101, but I don't understand this: Why do the voltages at the "Q" pins ADD together? If each stage's Q-pin is switched either LOW or HIGH and we imagine the output sees high impedance, it seems like the output would be either LOW or HIGH also. I don't see why the voltages of the stages end up being the sum of all the Q-outputs run through their resistors.

 

It's just plain Kirchhoff.
Call the stage outputs V1, V2, V3, V4 and V5 and the final output Vo. Call the resistor in each output R1 to R5
The current through each resistors is (V1-Vo)/R1 etc.
(V1-Vo)/R1 + (V2-Vo)/R2 + (V3-Vo)/R3 + (V4-Vo)/R4 + (V5-Vo)/R5 = 0
So Vo is somewhere between Vdd and Vss, depending on how many outputs are high and how many are low, and what resistances are between them.
If all outputs are high, then the output voltage is at Vdd. If they are all low, then the output voltage is Vss. All other states have some outputs high and some low.
The circuit stops being "digital" at the point that currents flow from outputs through resistors!
I bet if you're being smart about it, you could connect the five output resistors to the input of a MFB filter, which is a virtual earth.

 

It's just plain Kirchhoff.
Call the stage outputs V1, V2, V3, V4 and V5 and the final output Vo. Call the resistor in each output R1 to R5
The current through each resistors is (V1-Vo)/R1 etc.
(V1-Vo)/R1 + (V2-Vo)/R2 + (V3-Vo)/R3 + (V4-Vo)/R4 + (V5-Vo)/R5 = 0
So Vo is somewhere between Vdd and Vss, depending on how many outputs are high and how many are low, and what resistances are between them.
If all outputs are high, then the output voltage is at Vdd. If they are all low, then the output voltage is Vss. All other states have some outputs high and some low.
The circuit stops being "digital" at the point that currents flow from outputs through resistors!
I bet if you're being smart about it, you could connect the five output resistors to the input of a MFB filter, which is a virtual earth.

Let's see if I understand you correctly: if V1 is high and V2-V5 are low, then current out the V1 pin is being sunk at pins V2-V5?

 

Here is a thought: You can use a CD4046 , employing one of the edge sensitive phase detectors (I recommend the Fairchild version which is much more stable than the other edge sensitive phase comparator) that has an RS flip-flop as the phase detector and place no divider in the feedback. That way the CD4046 will reproduce the incoming frequency. The trick is to adjust the two resistors to ground on the VCO to obtain the duty cycle that you desire. Alternatively you could use a one-shot but that would reduce the elegance.

 

Let's see if I understand you correctly: if V1 is high and V2-V5 are low, then current out the V1 pin is being sunk at pins V2-V5?

That's it. If all the resistors were the same value (I know they're not, but it makes it easier to think about), then the output would be a fifth of the way between Vss and Vdd.