@Hypatia's Protege @crutschow @OBW0549 @Alec_t and anyone else who can help understand Ltspice!

If I run Ltspice on HP's modification from post 13 the opamp inputs stay exactly equal all through simulation even though output climbs and settles like it should! So how can that be? For screen capture I set vertical axis tick to 1 picosecond and input voltages still exactly coincide!

So + and - inputs are equal for first 3ms during powerup while they rise from 0v to reference (which is totally ok cuz it's just how V1 is modeled) but then they both totally stay equal to reference for entire simulation! Now I have to say I don't get it cuz if it's just due to offset how can circuit work even in simulation (which it does)! So I'm confused but I promise to be patient w/o attitude cuz I hope to learn Ltspice too!

 

HP Sry to throw ice water on this (which I should be saving for JC anyhow) but however you do phase compensation I say you need lower reference voltage cuz 4.7V isn't convenient for zaptraps made of, like you are thinking, just diode connected jfets! Cuz I say that gives guaranteed margin of 0.4V and developing special rails just for zaptrap returns is totally bogus!

HP protecting opamp input from transients is more than just _good idea_ it's totally necessary! Even if fb is from just single path from output of rectifier filter through divider (which is like in post 7)

So I can't find discrete Zeners with Vz < 1V so I say since opamp input is super high z so also super buffered you can just use higher voltage ZD and resistive divider for reference of like 0.3V

I hear ya! -- Unfortunately a simulation with so small an Eref would run for days on my fastest machine (unless there be a 'trick' I ignore) -- That said, I should think merely 'hanging' the transient clippers 'around' the Gnd and +10V rails (i.e. each 'side' of the input) should suffice?

@Hypatia's Protege @crutschow @OBW0549 @Alec_t and anyone else who can help understand Ltspice!

If I run Ltspice on HP's modification from post 13 the opamp inputs stay exactly equal all through simulation even though output climbs and settles like it should! So how can that be? For screen capture I set vertical axis tick to 1 picosecond and input voltages still exactly coincide!

So + and - inputs are equal for first 3ms during powerup while they rise from 0v to reference (which is totally ok cuz it's just how V1 is modeled) but then they both totally stay equal to reference for entire simulation! Now I have to say I don't get it cuz if it's just due to offset how can circuit work even in simulation (which it does)! So I'm confused but I promise to be patient w/o attitude cuz I hope to learn Ltspice too!

Can it be! -- Aleph stymied by (what amounts to) a filter design problem?! Thus it seems the dominant Pole herself is in need of compensation

Well hey! -- lame plays on words aside - I'm pleased I'm not the only one confused by Spice!

I promise to be patient w/o attitude cuz I hope to learn Ltspice too!

Me as well! --- Hang in there!

Very best regards
HP

 

I set vertical axis tick to 1 picosecond and input voltages still exactly coincide!

Ummmm... I think you mean one picovolt But YES! I see what you mean!

Very best regards
HP

 

o + and - inputs are equal for first 3ms during powerup while they rise from 0v to reference (which is totally ok cuz it's just how V1 is modeled) but then they both totally stay equal to reference for entire simulation. ! Now I have to say I don't get it cuz if it's just due to offset how can circuit work even in simulation (which it does)! So I'm confused...

If the two input voltages were significantly different than the op amp output would be saturated.
As long as the op amp output is not saturated at one of the rails and stays in the linear region, then that means the two input must be nearly equal to each other expect for input offset and the output voltage divided by the gain.
The LT1677 has the following specs:
■ Offset Voltage: 60µV Max
■ High AVOL: 7V/µV Min, RL = 10k

So even for a 7V output, the maximum difference in the two input voltages would by 60µV+1µV=61µV.
That will look pretty darn close to 0V (I measure 8µV in my simulation).

The reason the input voltage stays constant during the startup is due to the compensation negative feedback through C4, which basically keeps the op amp in its linear region without saturating even though the error signal from the output is changing as the output voltage rises.
If you look at all the currents into the op amp summing (-) junction from all the feedback and error signals, they will sum to zero, also indicating operation of the op amp is in the linear region.

Look at the op amp output during the simulation and you will see what is happening.

All make sense?

 

Thus it seems the dominant Pole herself is in need of compensation

I think you mean one picovolt But YES! I see what you mean!

HP that's right! Sry!

That will look pretty darn close to 0V (I measure 8µV in my simulation).

Thx @crutschow but how do you measure that? Cuz when I set y-axis for 1pV per _tick_ (like in capture in post 21) input traces are still totally coincident

Look at the op amp output during the simulation and you will see what is happening.

So it climbs aprx linearly to abt 5V for first 3ms (so that's during V1 power up). Then it descends to abt 2.1V during next 800us which is really just initial LF component of ringing that's totally damped out in abt 5.6ms to ≈ 2.46V flatline which doesn't change very much anymore all the way to lock. So that's in range of what I'd expect for opamp output but I don't understand why I can't see voltage difference between inputs no matter what I do Cuz I should easily see 8uv with super fine 1pv setting So I know I'm doing something wrong I just don't know what

Anyhow big thanks for helping out!

 

Thx @crutschow but how do you measure that? Cuz when I set y-axis for 1pV per _tick_ (like in capture in post 21) input traces are still totally coincident

You plot the difference voltage.
During or after the simulation, left-click on one of the inputs and hold the button down.
Move the pointer to the other input and release.
That will plot the difference voltage.

In general, you can right-click on any plot variable, and then add an equation in the window to do all types of waveform arithmetic (look up waveform arithmetic in the Help file).

 

You plot the difference voltage.
During or after the simulation, left-click on one of the inputs and hold the button down.
Move the pointer to the other input and release.
That will plot the difference voltage.

In general, you can right-click on any plot variable, and then add an equation in the window to do all types of waveform arithmetic (look up waveform arithmetic in the Help file).

Sweet! -- Thanks @crutschow ! - I'm bound to say Spice is showing much more promise now that I'm deigning to actually study it's correct use

@Aleph(0) --- This is to draw your attention to post #26

Best regards
HP

 

I'm bound to say Spice is showing much more promise now that I'm deigning to actually study it's correct use

Glad to hear that.
I think that much (but not all) of the negative comments about Spice simulators comes for those who have used it only infrequently, and have had some bad experiences due to not understanding some of the subtleties and limitations of its operation.
It's like any complex tool.
If you don't know how to use it properly, you will likely get some bad results and hit some sour notes.
Every heard a beginner on a violin?

 

You plot the difference voltage.
During or after the simulation, left-click on one of the inputs and hold the button down.
Move the pointer to the other input and release.
That will plot the difference voltage.

Crutschow tnx! That works great!

In general, you can right-click on any plot variable, and then add an equation in the window to do all types of waveform arithmetic (look up waveform arithmetic in the Help file).

Crutschow how do you do that? Cuz when I Rt-click on node I can't find anyway to paste to window? So is there special window I need to open? TNX!

 

Cuz when I Rt-click on node I can't find anyway to paste to window?

Hey Aleph -- here's how it works (Please note: other means to the end likely exist!)
1) Having drafted the schematic, run the simulation.
2) Create a trace via placement of a probe or probes on the schematic.
3) Right click a node name on the 'scope' window.
4) Arrange the desired equations in the resulting 'expression editor'.
5) Left click 'OK'.

Very best regards
HP

 

Crutschow how do you do that

HP covered it.
You do it in the plot window, not the schematic window.
It has to be a node that you have already plotted.