I have a Digilent CMOD A7-35T FPGA module. I am programming it in VHDL via Vivado V2019.1. I have been using the on-board XADC that has two channels going to the CMOD connector. The CMOD drops these voltages from 0-3.3V to 0-1V for the FPGA via the following circuit:


AIN15 and AIN16 are inputs from the CMOD connector and are 0-3.3V analog inputs. As shown they are scaled down to 0-1V inputs for the Artix-7 XADC FPGA. Where we use the XADC VAUX4 or VAUX12.

This was working fine in the field for a day or two and then suddenly started returning 0 ADC counts or (0 Volts). I checked the voltage on the pin of the CMOD and it is there as expected. I checked the impedance from the pin to ground and got 3.3K ohms as shown above also as expected. So the voltage is getting to the pins, and the pins appear properly connected to the boards internal voltage divider resistors. I as originally using AIN15. When it stopped working, I changed the circuit and the firmware to use AIN16. That also did not work, though again the voltage is at the pin and the resistance from the pin to ground is correct, that is around 3.3K.

Here is the xdc file entries for the pin. By commenting in or out I can use either AIN15 or AIN16:


## Analog XADC Pins
## Only declare these if you want to use pins 15 and 16 as single ended analog inputs. pin 15 -> vaux4, pin16 -> vaux12
#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { xa_n }]; #IO_L1N_T0_AD4N_35 Sch=ain_n[15]
#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { xa_p }]; #IO_L1P_T0_AD4P_35 Sch=ain_p[15]
set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { xa_n }]; #IO_L2N_T0_AD12N_35 Sch=ain_n[16]
set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { xa_p }]; #IO_L2P_T0_AD12P_35 Sch=ain_p[16]

Here is the VHDL that was working just fine for a good while:

I used Xilinx IP to create the XADC component and set it up for single channel use.

Am I doing something wrong in the firmware that might cause it to be intermittent or is there something else that I might be doing wrong.

Thanks for any help in advance.

 

Update:
AIN16 is now working. I did not change the register address from 0x14 (for AUX4) to 0x1C (for AUX12). The original channel though is still not working, so it appears to be specific to that channel.

 

Update:
It now appears to actually be an intermittent startup issue with the firmware. I have implemented a 'delay' after the FPGA starts up before trying to read the XADC. It is working at the moment and time will tell if this is the 'final' fix.