The original schematic looks like buttons 1-4-7 have to be held down together, no pressed in any particular order. There is no memory element involved to remember that the 1 was pressed before the 4, for instance.

The diodes around the AND gates make them remember the high input, and that is passed along the string of gates. If you press any other key it clears that memory and you would have to start again with the correct sequence.

 

It still probably won't work even with the 1k resistors though. The output source current of 74LS is only 0.4mA so that won't make a logic '1' level of 2V with a 1k resistor to ground.

Without some major redesign I fear the only solution is to use the intended CMOS gates.

 

The diodes around the AND gates make them remember the high input, and that is passed along the string of gates. If you press any other key it clears that memory and you would have to start again with the correct sequence.

Ah, I see. Hadn't looked closely enough. Clever little latching action.

It still does not quite require that they be in that sequence. For instance, pushing 1-7-4-7 should work (if I'm finally interpreting it correctly).

 

It still does not quite require that they be in that sequence. For instance, pushing 1-7-4-7 should work (if I'm finally interpreting it correctly).

Yep, as long as you don't press any numbers other than 1, 4, or 7,

 

It still probably won't work even with the 1k resistors though. The output source current of 74LS is only 0.4mA so that won't make a logic '1' level of 2V with a 1k resistor to ground.

I don't understand that.
0.4mA through 1kΩ is 0.4V which is below the logic "0" maximum voltage.

 

I don't understand that.
0.4mA through 1kΩ is 0.4V which is below the logic "0" maximum voltage.

Yes, 1k is fine for pulling an input below logic '0' level. The problem is that the AND gate output has to be able to pull the input, via the diode, up to 2V to hold the logic '1' state but the LS output can only supply 0.4mA so with the 0.4mA from the input makes just 0.8mA through the 1k - a long way from the 2V needed.

 

Gotta buy parts again then...thanks for the help. Ill come crying here if it doesnt work still hahaha

Yes, 1k is fine for pulling an input below logic '0' level. The problem is that the AND gate output has to be able to pull the input, via the diode, up to 2V to hold the logic '1' state but the LS output can only supply 0.4mA so with the 0.4mA from the input makes just 0.8mA through the 1k - a long way from the 2V needed.

To summarize all that ive read though..
Change out the resistors..but it might not output 1 anymore?

 

Yes, 1k is fine for pulling an input below logic '0' level. The problem is that the AND gate output has to be able to pull the input, via the diode, up to 2V to hold the logic '1' state but the LS output can only supply 0.4mA so with the 0.4mA from the input makes just 0.8mA through the 1k - a long way from the 2V needed.

That makes sense.
I misunderstood your original statement.

So I don't seen any solution but to go to the C or HC CMOS versions of the logic gates with that circuit.

 

Ah ok, guess the projects kaput then. Thanks for all the advice, much appreciated

 

To summarize all that ive read though..
Change out the resistors..but it might not output 1 anymore?

Yes. It would still work if you press 1,4, and 7 simultaneously though.

 

Ah ok, guess the projects kaput then

Not so hasty!
Simulation shows that pull-down resistors in the range 2k2 - 3k3 on the gate inputs should work with the LS logic. Lower values will work, providing pull-up resistors are used on the gate outputs. For example, with a 1k pull-down resistor a pull-up in the 1k - 4k7 range should work.

 

Not so hasty!
Simulation shows that pull-down resistors in the range 2k2 - 3k3 on the gate inputs should work with the LS logic. Lower values will work, providing pull-up resistors are used on the gate outputs. For example, with a 1k pull-down resistor a pull-up in the 1k - 4k7 range should work.

Yes, that's a good trick. 74LS outputs have plenty of sink current.

 

Not so hasty!
Simulation shows that pull-down resistors in the range 2k2 - 3k3 on the gate inputs should work with the LS logic. Lower values will work, providing pull-up resistors are used on the gate outputs. For example, with a 1k pull-down resistor a pull-up in the 1k - 4k7 range should work.

So....correct me if im getting this wrong...i should put a 1k at the input..like the original diagram...and add another resistor at the output gate? With the diode?

 

The original diagram showed 10k resistors, which won't work.
If you use a 2k2-3k3 resistor at each AND gate input you shouldn't need additional resistors.
If you use 1k resistor at the inputs then a respective 1k-4k7 resistor from each AND gate output (i.e. before the diode) to the +ve rail should work. Your mileage may vary.

 

The original diagram showed 10k resistors, which won't work.
If you use a 2k2-3k3 resistor at each AND gate input you shouldn't need additional resistors.
If you use 1k resistor at the inputs then a respective 1k-4k7 resistor from each AND gate output (i.e. before the diode) to the +ve rail should work. Your mileage may vary.

I would go with 1kΩ resistors at the input and output.
Using only a single resistor on the input seems rather marginal, given the gates limited output current spec.

 

Hmmm ill try then..thanks as always