hi luca,
This is the conventional way to cancel out +/- Voffset on the Vout.
Assume the +/-Vsupplies are stable.
E
View attachment 269169

Thanks! I've a couple of questions:

I tried this circuit solution and it decreased the offset. In fact, before Vout was [0.5 ... 5]V and now Vout is [0 ... 4.5]V ... but I've the same problem
Now I should add 0.5V only to the 4.5V, not also in the 0 .. I need to measure a Vout = [0 ... 5]V.
1) What could I modify in your circuit? (I hope I have explained the problem well)

2) What is the purpose of the 100nF capacitor (C3 in your schematic) you inserted between the non-inverting input and gnd?

3) If I decided to remove the amplifier and connect the potentiometer network directly to the 2.2k resistor ...
I know that I would not have the high input impedance of the amplifier to "isolate" the potentiometer side with the instrumentation amplifier side. But what other problems would I encounter?
(I simulated and it still works the circuit)

 

hi luca,
C3 is for noise reduction from the +/-12V supplies entering into the Vref voltage.

To change now Vout is [0 ... 4.5]V ... to 0v +5Vout, slightly increase the Gain, reduce the 180R to say 175R as an initial test.
I would have made the 180R as say a 150R resistor in series with a 100R trim point, in order to set the Gain.
E

 

hi luca,
Check this out.
E

 

Hello again,

This is the other solution i was talking about. This preserves the common mode behavior and makes sure the output offset is only whatever the op amp input offset is, so if the input offset is 3mv then the output offset will only be 3mv after adjustment if the output of the previous section was adjusted for. if the entire offset is adjusted then it should be zero. The drift will still match the last op amp except the drift of the previous op amps will be amplified somewhat. The LM358 has pretty good drift characteristics though so should be ok.

The two resistors Rx should be the same, maybe 2.2k to 10k.
The two resistors Rp should be the same, maybe 10k each, and the pot 10k also but depends how much offset you have to adjust for.

Thanks for the circuit and the clear explanation!
But I refer you to the answer I gave to @ericgibbs in post #61.

In the circuit you sent me Vout = [0.5 ... 5]V, but I would need Vout = [0 .. 5]V. Voffset is added to both the left end of Vout (i.e., 0.5V) and the right end of Vout (i.e., 5V).

 

hi luca,
Check this out.
E
View attachment 269214

I attach my LTspice files so you can check what is wrong with my simulation, because it's different from yours.

 

hi luca,
Please post your plot.
E

 

hi luca,
This is your circuit with my Pot.
Is your pot orientated correctly.?
E

 

Thanks for the circuit and the clear explanation!
But I refer you to the answer I gave to @ericgibbs in post #61.

In the circuit you sent me Vout = [0.5 ... 5]V, but I would need Vout = [0 .. 5]V. Voffset is added to both the left end of Vout (i.e., 0.5V) and the right end of Vout (i.e., 5V).

Hello,

You will have to clarify that. Left end of Vout and right end of Vout, doesnt make any sense, there is only one Vout

 

hi luca,
This is your circuit with my Pot.
Is your pot orientated correctly.?
E
View attachment 269227

 

hi luca,
As I said, your Pot is the opposite way around in your circuit compared to mine.
Either Rotate the Pot through 180 degrees OR change the setting to 0.6.
CHANGE the wiper of the Pot so that the Vout is 0v, It is a Zeroing Pot.!
This is an example of the circuit with the pot rotated
E
.
E

 

hi,
With the Pot in your circuit set to 0.6 it gives the correct Vout.
E
Devi impostare il valore del piatto in modo che il Vout inizi da 0v

 

hi luca,
This shows the effect of stepping the Pot setting.
E

 

hi luca,
This shows the effect of stepping the Pot setting.
E
View attachment 269273

Unfortunately, I still can't figure it out, but these days I will test it in the lab and take measurements directly on the breadboard with the oscilloscope. I still attach a couple of screenshots on the simulation if you want to check where the error is ... but as I said, I will test it directly in the lab.

In any case, thank you both for your helpfulness and for your clear and quick answers.

With the Pot in my circuit set to 0.6 it gives this Vout:



With .step param wp .2 .6 .1 I see this:

 

hi luca,
The plots you post suggest that there is a problem in your set up.
The plot should not flatten out at 100mSec.??

Please post the full picture of the circuit diagram and the asc file.

E

 

hi luca,
The plots you post suggest that there is a problem in your set up.
The plot should not flatten out at 100mSec.??

Please post the full picture of the circuit diagram and the asc file.

E

I've just fixed the problem, now I see [0 .. 5]V. Last question, what is the porpouse of C3?

 

hi luca,
Good news!

Explained in post #63.
C3 is for noise reduction from the +/-12V supplies entering into the Vref voltage.

What was the problem you found.???
E

 

hi luca,
Good news!

Explained in post #63.
C3 is for noise reduction from the +/-12V supplies entering into the Vref voltage.

What was the problem you found.???
E

I had set an incorrect .tran simulation value

 

hi luca,
Good news!

Explained in post #63.
C3 is for noise reduction from the +/-12V supplies entering into the Vref voltage.

What was the problem you found.???
E

I've just opened a new thread because a friend lent me an INA118. If you want to take a look I'll leave you the link to the thread:

https://forum.allaboutcircuits.com/threads/ina118-amplifier-application.187461/

 

Hello,

You will have to clarify that. Left end of Vout and right end of Vout, doesnt make any sense, there is only one Vout

I've just opened a new thread because a friend lent me an INA118. If you want to take a look I'll leave you the link to the thread:

https://forum.allaboutcircuits.com/threads/ina118-amplifier-application.187461/