Alcom decoder

Thread Starter

geoffers

Joined Oct 25, 2010
496
Hi all,

While since I've posted here, I've been trying to repair a board made by delaval.

It suffered a failed voltage regulator which cooked a couple ic's some I can get one I can't.

The chip in question sits on delavals own bus system and drives/decodes the signals for the main processor on each node. The bus signal is on 2 wires and differential. Biphase Manchester encoded, I was just trying to decide how to decide it when I came across the circuit below online, just wanted to check I'd understood how it works correctly?Screenshot_20221109-181708~2.png
As I've understood it, the signal comes in across r53/r56, the - input of the comparator is set to 1/2vcc by r58/59, effectively grounding the diff signal.
The output of the comparator is connected to Rx of a processor which has a weak pull up on it.
This and the comparator output through r52 hold the output high (UART idle)
R53/c61 and r56/c60 form RC timers, as the Manchester signal shows a zero with a high low transition in the middle of a bit period, the RC timers won't let the output change (low) unless there's a 1?

I'm not great at this stuff, have I interpreted it right? I'm probably going to use a pic16f1779 to do the job so could just use a onboard compater and timer to decode but thought this was interesting?!?

Thanks Geoff
 

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MrChips

Joined Oct 2, 2009
34,809
C60 and C61 are RF noise filters.
R58 and R59 create a weak bias of 1/2 Vcc at the inverting input.
R52 is positive feedback to the non-inverting input. This gives the comparator hysteresis.
Comparator ICs normally have open-collector outputs. They require a load resistor in order to realise voltage output. I would give it more than a weak pullup.
 

Thread Starter

geoffers

Joined Oct 25, 2010
496
Thanks, I'd got the wrong end of the stick! I've just gone back over my sums and n seen I was a decimal place or two out!

The bit period of the Manchester signal is 16uS and I'd worked out the RC time period as 10uS (just over half a bit period) and thought the comparator was demodulating the signal to a serial signal the processor could interpret.
IMG_20221121_151246_048.jpg
Here's the signal if anyone's interested once demodulated comes out as 9 bit serial
 
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