Facebook
Google
GitHub
Linkedin
Hi All,
I recently posted a threat regarding transferring the data output from a 50MS/s 16 bit ADC to a PC and got a lot of very useful answers! (https://forum.allaboutcircuits.com/threads/getting-data-from-adc-output-to-pc.166190/)
I'm trying to break this project down into simpler individual parts and build up from there.
I've spent the last week learning about and trying to come up with some designs for a driver cicruit which will take the stream of voltages from my sensor( Hamamatsu S11105) and prepare them to be digitized using the full range of the ADC (https://www.ti.com/lit/ds/symlink/ads5562.pdf).
The goals for the circuit are as follows:
The input signal is an analogue voltage which has a base or offset of 1.2V (corresponding to no light hitting the corresponding pixel) and peaking at 2.5 V (corresponding to the pixel well being full).
This single ended voltage must be transformed into an LVDS signal which has a common mode voltage of 1.5 V The LVDS + and - voltages then oscillate around Vcm + and - 0.9V respectively with amplitudes of 0.9 V That means on the plus side the voltage can be as high as 3.3V and as low as 1.5 V, while on the negative side, the voltage can be between 1.5 V and -0.3 V. Differential voltages of + = 3.3V and - = -0.3V (Diff = 3.6 V) would correspond to the highest possible value into the ADC and both equalling 1.5 V (Diff = 0V) would correspond to the lowest posible value into the ADC.
I've come up with a first pass at a potential driver circuit (ignoring the layout for the moment) by having read through the extensive manuals that TI and running a simulation in LTSpice. (See attached circuit and the .asc file) The circuit first gets rid of the 1.2 V bias by AC coupling the signal, then uses a high bandwidth differential Opamp which , mostly by tweaking the ratio of the input and feedback resistors, supplying a suitable common mode voltage of 1.5 V and placing a 6.8 pF cap between the LVDS + and - channels, seems to nearly achieve the desired effect (within the limits of the simulation).
The input signal I've used is a sine wave oscillating between 1.2 and 2.5 V at 50 MHz (this would correspond to every pixel being full) but I've also tried this with half full and pixels (oscillating between 1.2 and 1.85 V) and it worked consistently.
I've also attached some traces, the Green trace corresponds to the input signal, and the red and blue and red traces are the voltage sampled between R8 and C3 and R9 and C3, respectively.
There are a couple of things I've noticed about this that I'm not sure how to solve and I hope the community might be able to advise on. First is that the LVDS traces, while just about correctly reaching their maxima and minima at 3.3V and -0.3V seem to have a significant gap where they don't touch which should correspond to 0V. This isn't the biggest problem as it still uses >90% of the ADC input but, of course it'd be best to maximise this.
The second is that the signal appears to have picked up a phase shift of approximately half a cycle and the peaks appear where the minima should be and vice versa.
Other than that, I realise this is a simulation, and certainly won't capture all the nuances of reality so If you see any other issues I need to address I'd be very glad to hear them!
I recently posted a threat regarding transferring the data output from a 50MS/s 16 bit ADC to a PC and got a lot of very useful answers! (https://forum.allaboutcircuits.com/threads/getting-data-from-adc-output-to-pc.166190/)
I'm trying to break this project down into simpler individual parts and build up from there.
I've spent the last week learning about and trying to come up with some designs for a driver cicruit which will take the stream of voltages from my sensor( Hamamatsu S11105) and prepare them to be digitized using the full range of the ADC (https://www.ti.com/lit/ds/symlink/ads5562.pdf).
The goals for the circuit are as follows:
The input signal is an analogue voltage which has a base or offset of 1.2V (corresponding to no light hitting the corresponding pixel) and peaking at 2.5 V (corresponding to the pixel well being full).
This single ended voltage must be transformed into an LVDS signal which has a common mode voltage of 1.5 V The LVDS + and - voltages then oscillate around Vcm + and - 0.9V respectively with amplitudes of 0.9 V That means on the plus side the voltage can be as high as 3.3V and as low as 1.5 V, while on the negative side, the voltage can be between 1.5 V and -0.3 V. Differential voltages of + = 3.3V and - = -0.3V (Diff = 3.6 V) would correspond to the highest possible value into the ADC and both equalling 1.5 V (Diff = 0V) would correspond to the lowest posible value into the ADC.
I've come up with a first pass at a potential driver circuit (ignoring the layout for the moment) by having read through the extensive manuals that TI and running a simulation in LTSpice. (See attached circuit and the .asc file) The circuit first gets rid of the 1.2 V bias by AC coupling the signal, then uses a high bandwidth differential Opamp which , mostly by tweaking the ratio of the input and feedback resistors, supplying a suitable common mode voltage of 1.5 V and placing a 6.8 pF cap between the LVDS + and - channels, seems to nearly achieve the desired effect (within the limits of the simulation).
The input signal I've used is a sine wave oscillating between 1.2 and 2.5 V at 50 MHz (this would correspond to every pixel being full) but I've also tried this with half full and pixels (oscillating between 1.2 and 1.85 V) and it worked consistently.
I've also attached some traces, the Green trace corresponds to the input signal, and the red and blue and red traces are the voltage sampled between R8 and C3 and R9 and C3, respectively.
There are a couple of things I've noticed about this that I'm not sure how to solve and I hope the community might be able to advise on. First is that the LVDS traces, while just about correctly reaching their maxima and minima at 3.3V and -0.3V seem to have a significant gap where they don't touch which should correspond to 0V. This isn't the biggest problem as it still uses >90% of the ADC input but, of course it'd be best to maximise this.
The second is that the signal appears to have picked up a phase shift of approximately half a cycle and the peaks appear where the minima should be and vice versa.
Other than that, I realise this is a simulation, and certainly won't capture all the nuances of reality so If you see any other issues I need to address I'd be very glad to hear them!
