Hello, I'm trying to design a circuit using the SN74AHCT1G08 AND gate. DigiKey lists the high-level input voltage as 2V, but in my simulation, the gate output voltage remains at the “low” level even at 2V. Why is this happening?

 

the gate output voltage remains at the “low” level even at 2V. Why is this happening?

2V is the transition logic level and the model may expect a voltage slightly higher than that for a high output (perhaps at least 2.5V).
Normal logic levels are 0V or 5V.
Why are you applying only 2V?

 

2V is the transition logic level and the model may expect a voltage slightly higher than that for a high output.
Normal logic levels are 0V or 5V.
Why are you applying only 2V?

I know it's 0 and 5V, but seeing that voltage range on DigiKey struck me as odd, so I wondered if my theoretical knowledge doesn't match my practical experience.

 

You're using a "SN74AHCT1G08" and the datasheet fragment is for a "74LVC". THEY ARE NOT THE SAME PART! My apologies for yelling.

 

I know it's 0 and 5V, but seeing that voltage range on DigiKey struck me as odd, so I wondered if my theoretical knowledge doesn't match my practical experience.

A Spice model can't/doesn't exhibit all the characteristics of a real device.
And the voltage spread for those switching parameters are for manufacturing variations, which occur between different units or manufacturing batches.

There is always some difference between device models and real devices, so a simulation will never exactly match a real circuits operation.

 

so you are lying to simulator (using HCT part but assuming LVC part) and expecting simulator to somehow catch it and tell the truth?


hmm, my bad. i fell into same trap - just checked and Vih threshold for both LVC and HCT is 2V so while not a good idea to sit on the very edge, this should work.


here is document from TI on this:
https://www.ti.com/lit/an/scla011/scla011.pdf

 

this should work.

What is "this"?
Certainly not the simulation.

 

What is "this"?
Certainly not the simulation.

why not?

if the model is correct for 74HCT, then for Vcc=5V input voltages greater or equal to 2V should be interpreted as logic 1.
last i checked 2.000V >= 2 evaluates as true hence logic 1

since logic gate is AND, and inputs are true, output should be true as well, and therefore reach at least 2.4V

here one from Wikipedia/TI:
.

 

why not?

Because simulated models typically use "typical" not worst-case values.
Thus, for example, my Spice models for the 74HCxxx logic family uses 1/2 the supply voltage as the logic-level change-state values, which is likely typical of that CMOS family (sim below for Vcc=5.5V):

 

yes but that is HC and not HCT series. they have different thresholds.
HC, AHC and AC are symmetrical (as seen in #8) while TTL compatible HCT, AHCT, ABT and ACT are not.

 

yes but that is HC and not HCT series. they have different thresholds.

Yes.
But don't know how well the Spice models track that.

 

I think post #10 and #11 are both correct.
Apparently, the (PSpice) model doesn't simulate the behavior of being driven by TTL input levels.
An easy way to check is for the OP to change the input levels to 5v CMOS levels and verify it works correctly.

 

Yes.
But don't know how well the Spice models track that.

exactly what i said:

if the model is correct for 74HCT,...

 

exactly what i said:

So I seemed to have missed your point.
It is known that most Spice models don't use worst-case values, which are the values you are showing.
So what, exactly, is a "correct" model?

 

correct model would be one that faithfully replicates real device behavior.

in this case we are looking at thresholds.
per datasheet Vih = 2V and Vil=0.8V...

so 2V or 2.1V or 2.2V should all be seen as logic 1.
0.8V or 0.6V or 0.1V should be seen as logic 0.
and 0.9V is indeterminate, likely to be seen as 0 but not guaranteed.
and 1.9V is also indeterminate, likely to be seen as 1 but not guaranteed.

 

correct model would be one that faithfully replicates real device behavior.

True.
But you are misinterpreting what the spec says about that.

so 2V or 2.1V or 2.2V should all be seen as logic 1.
0.8V or 0.6V or 0.1V should be seen as logic 0.

Those are worst-case values which imply a large hysteresis in the input operating point, but that does not occur in a real device (except those few which are purposedly designed with hysteresis).
If you test a real device you will see that the output transition occurs over just a few tenths of a volt input voltage change (depending upon the logic circuit type and its open-loop gain of 6-15 for TTL and 10-50 or more for CMOS).
So a simulation compromise nominal value is used with the 0 and 1 logic levels essentially identical.
That's inconsequential for most digital simulations where the input goes from near zero to the high logic-level.

 

thank you for elaborating but i think you are misinterpreting what i understand. when i started playing with TTLs (long time ago) i did explore just this and wanted to confirm how outputs are following input (tie gate inputs together, manually adjusted input voltage, while monitoring output). and while i did not try extensive tests like temperature effects, variations in supply etc, I do know first hand since i was teenager that tipping point is a around middle of indeterminate range and not very accurate from one gate to another. but it splits input to one or another level. what you describe matches this (so far).

this datasheets say that for this logic family input thresholds are 0.8V (low) and 2V (high). that is not questionable.
so 2.000V input shall be seen as logic 1 - no ifs and buts. and yes, i do know that 2V is extreme:

...not a good idea to sit on the very edge...

so since logic element is an AND gate, and both inputs are at logic 1, the output should also be logic 1 (with output voltage getting near Vcc, which is 5V). yet the simulation shown by TS shows that output is dead zero, which is wrong. because this does not follow datasheet levels nor expectations, to me this means one thing - that sim is wrong. that outputs would be appropriate for NAND or NOR gate, so simulation is for wrong gate or for defective AND gate.

and the only thing i am not sure about is what makes you think that this simulation is ok. why do you think that logic 0 is correct output in this case?

i don't have any HCTs on hand but i am pretty sure that if i wire one it would do what i was describing, not what simulation output shows.

 

datasheets say that for this logic family input thresholds are 0.8V (low) and 2V (high). that is not questionable.

Yes, we've established that.
But it is questionable as to how would you set up a simulator for that without creating an abnormal amount of hysteresis.
Whatever you do, you can't simulate both worst-case logic levels with one model.
Is that not clear?

 

pardon my ignorance but i really do not know (or care) what it is under the hood of a spice simulator. or why comparing input voltage against fixed levels need hysteresis at all on a gate that is not Schmidt trigger...

whatever the approach is, that is something that simulator creators should take care of. the whole point of simulation is to model real world and if it cannot do that well, that it is not a good simulation.

 

Yes, we've established that.
But it is questionable as to how would you set up a simulator for that without creating an abnormal amount of hysteresis.
Whatever you do, you can't simulate both worst-case logic levels with one model.
Is that not clear?

Actually, you could using one model, by using params to setup the thresholds.