555 Timer Operation Explanation

Thread Starter

crutschow

Joined Mar 14, 2008
31,148
For those interested, I have posted a simple diagram and description of the 555 Timer Functional Operation <MOD: broken link removed, please see content below>
 
Last edited by a moderator:

Thread Starter

crutschow

Joined Mar 14, 2008
31,148
Here's a copy of my post--

The 555 timer is one of the most widely used analog ICs ever made, but its principles of operation are not always clear from the data sheet, so here's a short, and hopefully clearer, explanation of that.

------------------------------
1660407727281.png

1661101297810.png


The 555 operation is fairly simple.
It is basically a level-triggered flip-flop (latch) with an added DIScharge output to reset the timing capacitor.
The trigger levels are determined by the three 5kΩ voltage divider resistors (apparently where the 555 designation came from).
  • When the TRIGger voltage goes below 1/3 Vcc, (and the THRS voltage is below 2/3 Vcc), the FF is Set (OUTput high and DIScharge open).
  • When the THRShold voltage goes above 2/3 Vcc (and the TRIG voltage is above 1/3 Vcc), the FF is Cleared (OUT low, and DIScharge connected to ground by the transistor to discharge the timing capacitor).
  • The RST (Reset) terminal Clears the FF when driven low (<0.5V). It can be connected to Vcc for normal operation.
  • The CV (Control Voltage) terminal is connected between the top two resistors of the three internal 5kΩ voltage divider resistors that determine the 1/3 and 2/3 Vcc trigger points. It is typically used to add a 10nF capacitor to GND if there is a concern about Vcc noise affecting the 555 timing. It can also be used as an input to adjust the triggers points and thus the timing, for such applications as PWM (Pulse-Width-Modulation).
So if you understand the above, then it should be easier to understand the operation of the 555 in it's various modes of operation, such as astable and monostable multivibrator, or just being used as a level triggered latch.
 

Ian0

Joined Aug 7, 2020
6,728
I'll add the following:
1. TRIG overrides THRESHOLD, so if pin2 is <33% Vcc at the same time that pin 6 > 67% Vcc then the output will be high.
2. The maximum range of the CONTROL pin when used as an input claims to be the full supply voltage for the bipolar type. although it will stop oscillating when CONTROL exceeds the maximum output voltage.
It is specified at from 1V to Vcc for the CMOS types.
3. There is an error in the datasheet.
"9.2.2.1 Design Requirements: Clock input must have VOL and VOH levels that are less than and greater than 1/3 VCC."
Actually it must be greater than and less than half the voltage on pin 5.

Does anyone know the value of the "5k"resistors in the CMOS types?
 
Top