555 Timer monostable help needed

Thread Starter

leahcim4686

Joined Dec 18, 2020
5
I'm designing a timer circuit and the 555 IC has an unacceptable flaw. In monostable, if the trigger is held longer than the set time, the output will remain high until the trigger is released with no delay. This thread, https://forum.allaboutcircuits.com/threads/monostable-555-trigger-release-issues.113131/, has a solution that will cause the output go low after the set time, but my needs are different. I want a circuit that will output high while the input is high AND a set time after input goes low.
Truth table:
InputOutput
11
Falling edge1 until timer ends
0 (after timer ends)0

As I wrote this, I though of a solution; use the solution from the aforementioned thread with an OR gate from the 555 output and initial input.


If anyone has a better solution, I'd be happy to read it.
 
Last edited:

AnalogKid

Joined Aug 1, 2013
9,287
1. It sounds like what you want is called a pulse stretcher. Let's assume the circuit has a time constant of 2 seconds ...

Input goes high.
Output goes high immediately.
If the input goes low in 0.1 s, the output goes low in 2.1 s.
If the input goes low in 1.999 s, the output goes low in 3.999 s.
If the input goes low in 2.001 s, the output goes low in 4.001 s.
If the input goes low in 3.5 s, the output goes low in 5.5 s.

No matter how quickly or slowly the input is released, the output adds 2 seconds to it.

Does this sound like what you want? If yes, a 555 can do this; but so can a couple of gates or a couple of transistors.

What is the "set time" period you need? And, where are you located?

ak
 
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Ian0

Joined Aug 7, 2020
2,639
Does this sound like what you want? If yes, a 555 can do this; but so can a couple of gates or a couple of transistors.

What is the "set time" period you need? And, where are you located?

ak
If you're triggering it with a switch, and you have a double-pole switch, that would do the job. Connect the second pole across the timing capacitor!
If it's a single pole switch, then a diode between pin 2 and pin 6/7 will work (cathode to pin 2).
 

Ian0

Joined Aug 7, 2020
2,639
First you need to invert the signal, because the trigger on pin 2 is negative going
second, you need to prevent the timing capacitor from starting to charge until the device is released.
So, how about a couple of BS170 MOSFETs. Both gates to your device. Both sources to ground. One drain to pin 2, the other drain to pin 6/7. Pullup from pin 2 to V+.
 

Thread Starter

leahcim4686

Joined Dec 18, 2020
5
I hate sounding like a online so let me clarify in advance: I am considering your idea and comparing it equally with my own; in no way do I intend to judge or disparage you or your idea.
First you need to invert the signal...
The HMI has an option for high/low output so there's no need for an extra NOT gate.
Pullup from pin 2 to V+.
There's already a 100k pullup in parallel with the diode, does it need to bigger/smaller?
555.png
The HMI will essentially behave as a PB SPDT with the pole as the output (the button might be held for a few seconds to several minutes).
second, you need to prevent the timing capacitor from starting to charge until the device is released.
My idea is:
with the signal being normally low, the cap will keep pin 2 high
when the signal goes/is high, the cap will discharge while pin 2 stays high
when the signal goes low, the cap will send a short low pulse to pin 2

The HMI signal and pin 3 will go to an OR gate then to the relay.

If my knowledge of current flow is way-off, my idea won't work, otherwise, it seems simple. What's your assessment? Will the MOSFETs work better?

Thanks,
Leah
 

Ian0

Joined Aug 7, 2020
2,639
You said
AND a set time after input goes low.
What happens on your circuit is.
Input signal goes low - 0.1uF cap delivers a short pulse to pin2 and timing starts pin 3 goes high.
After the timing period is over pin 3 goes low, the output is still high because of the OR gate.
When the input signal ends, the output will immediately go low.

The second transistor prevents the timing capacitor charging up, so the timing period cannot start until the input signal has gone, so no OR gate is needed.

I'm guessing that
I'm triggering it with an HMI device; VOH=0.8VCC, VOL=0.3VCC
really means Voh>0.8Vcc, Vol<0.3Vcc, and it truth it's really a CMOS push-pull output, but please confirm.
 

crutschow

Joined Mar 14, 2008
27,408
Below is the LTspice simulation of an example 555 circuit that I believe does what you want:
The transistor keeps the timing capacitor low until the input goes back low.
It's shown for an input pulse length of 1s and 2s (Vin).
As you can see, for each input pulse, Vout going low is delayed about 5s after the end of the pulse.


1608398726087.png
 

Ian0

Joined Aug 7, 2020
2,639
HMI activated - output goes low. Capacitor discharges quickly via diode and 100 ohm resistor. 555 output goes high almost straight away. (100 ohm resistor is included for a bit of current limiting).
HMI deactivated - output goes high. Capacitor charges slowly via 100k resistor. After a time delay, 555 output returns low.
Isn't that what the TS wanted?
 

Ian0

Joined Aug 7, 2020
2,639
It's adjustable - that gem of information was hidden away in the middle of post #7.
If it were positive-going then reverse the diode, and the output is negative going, because the 555 inverts.
 

eetech00

Joined Jun 8, 2013
2,491
Ummm.....the requirements are in post #2.

If I understand the requirements, the timer shouldn't start timing out until the HMI returns to its un-activated state(?)
 
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