Hello.
Iam presently working on designing a basic multi level inverter.
Iam not explaining the working principle of the inverter.

I have a plan in which a few timers(555) are cascaded.
The process will be first initiated by a 555 astable whose duty cycle is 10%.
(5ms ON and 45ms OFF). the time period is 50ms.

For every 50ms, the process should repeat.

Now coming to the point, the first section timer should give a 15ms ON pulse.
This should be initiated by the astable 555 after 5ms.
Thats why i wired the astable to have 5ms ON pulse.

when i connected the output (3 pin) of astable 555 to triggering input (2 pin) of monostable 555, the output is simply inverting the triggereing signal.

Chek the attachment.

When iam varying the 47K pot also, the output(555 mono output) is not responding. The output is responding when iam adjusting the attributes of 555 astable.

Why the timing elements of 555 mono are not playing the role.

 

Bypass caps on the timers?

 

Bypass caps on the timers?

how?
shall i put 1n4148 parallel to the capacitor?

what is the reason?

 

Fundamentally a 555 is a inverting Schmitt Trigger, so it would make sense it is an inverter. Pin 7 is a discharge pin for the timing capacitor, which gets the process started.

Other that the above I've put no thought into the problem. I'm about to go to sleep.

 

how?
shall i put 1n4148 parallel to the capacitor?

what is the reason?

Just about every IC needs a 0.1µF capacitor near to it and across it's power pins, to absorb noise, inductive ringing, whatever. There's a link to the issue often referenced here, but I can't seem to spot it at the moment. Is that a diode you're asking about? No, you don't need that.

Also, try increasing the resistor to 5k or so, or removing it. You may not be pulling the trigger low enough to turn it off. Just a speculation. Do you have an oscilloscope? I've just now been using mine with a timer. I use free software and my computer's sound input as a crude oscilloscope. Works great as long as you're in the 5Hz-5kHz range, as you are.

And another thing: You haven't shown any connections to ground between the two timers. Do they share a ground?

 

Pin 2 is triggered by a neg. pulse, add cap., 1 nF, between astable & mono. Triggering will be on trailing edge of 5 ms pulse. Or- reconfigure astable for 45ms high & 5 ms low, triggering now will be leading edge.

 

There's a link to the issue often referenced here, but I can't seem to spot it at the moment.

This one? It is a sticky at the top of the General Electronics Chat section.

Decoupling or Bypass Capacitors, Why?

 

Pin 2 is triggered by a neg. pulse, add cap., 1 nF, between astable & mono. Triggering will be on trailing edge of 5 ms pulse. Or- reconfigure astable for 45ms high & 5 ms low, triggering now will be leading edge.

Bernard s right, the 555 needs a negative pulse to trigger the monostable. A high to Low level change won't work.

See that attach simulation. Is that the waveform that you want? My schematic is on the second picture. Instead of doing a 10% duty cycle astable osc I made a 90% duty cycle osc and invert the output with a transistor which is much easier.

Allen

 

Bernard s right, the 555 needs a negative pulse to trigger the monostable. A high to Low level change won't work.

See that attach simulation. Is that the waveform that you want? My schematic is on the second picture. Instead of doing a 10% duty cycle astable osc I made a 90% duty cycle osc and invert the output with a transistor which is much easier.

Allen

thankyou ABSF.

This is exactly what i want.

 

Pin 2 is triggered by a neg. pulse, add cap., 1 nF, between astable & mono. Triggering will be on trailing edge of 5 ms pulse. Or- reconfigure astable for 45ms high & 5 ms low, triggering now will be leading edge.

got it. Got anew thing about 555.