16 bit latch

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mailakshansh

Joined Jan 16, 2018
1
Hello,
I want to create a 16-bit latch: a load-enable bit and 16-bit data input and output values using ONLY AND, OR, NOT gates.
I understand this can be achieved with two times 8-bit or four times 4-bit latch.
Any leads or images that I can use to understand what is going on..?

Thanks!

Mod edit: Welcome to AAC! Your post was moved to its own thread rather than reactivate this old one:
https://forum.allaboutcircuits.com/threads/16-bit-latch.119893/#post-1225054
 
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Papabravo

Joined Feb 24, 2006
12,389
For a 1 bit latch you have signals D, Q, and G. When G is high, then Q=D and the latch is in transparent mode. When G goes low, then Q=Q, and the output is whatever the value of Q was one setup time earlier. If you make a Karnaugh map of this equation you will see an obvious, but redundant, covering term. Adding this term to the other two gives a 3 term SOP equation for a latch. Now just replicate 15 more times.
 

WBahn

Joined Mar 31, 2012
24,686
Hello,
I want to create a 16-bit latch: a load-enable bit and 16-bit data input and output values using ONLY AND, OR, NOT gates.
I understand this can be achieved with two times 8-bit or four times 4-bit latch.
Any leads or images that I can use to understand what is going on..?
It's unclear to me exactly what your constraints are. First you say that you want to do this using ONLY the three most basic gates, but in the next line you talk about using smaller latches as building blocks.

What are the limitations your design has to live within?

Do you understand how a 16-bit latch has to behave? What are all of your inputs? Just the data and a load-enable? Are these clocked?
 
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