As I slso misinterpret TS requirements. Your interpretation appears to be right after re-reading the thread. Sorry for arguing with you, but - hey - sometimes that’s for the better

Your comments did not come across as an argument. I find the most difficult part of participating in this forum is interpreting requirements. Especially if the original poster is not on-line and participating when the rest of us are active.

 

Thank you for all your advice, especially to Crutschow for the suggestion.
I will take a look and will get back to you as soon as I can.

Regards,

dj

 

I posted a similar question a couple of months ago, seeking a solution.

Since I am not familiar with Arduino, nor am I good at programming, I think the BCD counter is a better approach.

Since maximum clock frequency of CD4017 is limited to 5.5MHz, 74HCT390 is used to divide the 10MHz clock by 10. So could you elaborate on this approach?

Regards,

dj

Just keep in mind for future reference the posted design requires you type one
command, the start command, for code. Its not Arduino. And it has, for simple logic
designs, no required start command. So no code required. You drag and drop gates,
flops, etc. onto a canvas, "wire" them up with the tool to pins, hit the build button
and you have a design running.

Also you right click the component, and open its datasheet, and the instruction format
to type is directly in datasheet in case you forget.

From the arduino point of view, for future reference, there are visual programming
languages, like Ardublock, mBlock, Snap4Arduino, that 6'th graders are using to
do robot work. These tools also show you the C language it generates to familiarize
you with what basic C typing looks like. There are videos that help. In fact you can
look at scratch videos as the aforementioned tools are offshoot of Scratch.

http://www.mblock.cc/

Its fun. One step at a time. You don't have to climb mount Everest these days to
learn programming, you are already doing it in your head when you use a 4 function
calculator. Buy a cheap Arduino or Cypress board. the latter more capability overall,
the former more graphical as a programming tool.


Regards, Dana.

 

I posted a similar question a couple of months ago, seeking a solution.

What was wrong with the solutions presented in that thread?

ak

 

Here is my offering.

How accurate do you need the 100ns pulse?
R1 and C1 are added to delay the 100ns pulse. Without this delay there is a glitch after 1μs.
This delay causes the 100ns pulse to be about 110ns. You can also use the two spare AND gates to implement the delay.

The CD4017 works at 10MHz. I have not tested the upper frequency limit.
R2 is added to reduce ringing from the 10MHz crystal oscillator module.

 

Here is my offering.

How accurate do you need the 100ns pulse?
R1 and C1 are added to delay the 100ns pulse. Without this delay there is a glitch after 1μs.
This delay causes the 100ns pulse to be about 110ns. You can also use the two spare AND gates to implement the delay.

The CD4017 works at 10MHz. I have not tested the upper frequency limit.
R2 is added to reduce ringing from the 10MHz crystal oscillator module.

View attachment 179923

The glitch is almost certainly the result of not using a fully synchronous design and the delay is a patch thrown on to address a particular symptom that results on the system as was when it was tested.

The problem is that such symptoms may or may not be repeatable and the patch's effectiveness may similarly be hit and miss. Use components from a different batch or a different manufacturer or a different logic family or at a different temperature and the glitch may appear elsewhere (or not at all) and the delay needed might be different than the one that worked on the test system. The test system itself is also a variable. If it was breadboarded on a solderless breadboard, then the parasitics can start having noticeable affects at these frequencies. Changing the layout and routing can change the results of any critical races. It's quite possible that there glitches that the test system didn't exhibit because the races just happened to be decided in a fortuitous way but someone implementing it from the schematic may not be so lucky.

Sometimes glitch behavior (or at least some of the potential glitches) is predictable allowing remediation to be designed that works over all the operating variables. But even when this is the case, it generally requires careful analysis and design.

 

It seems like the best approach is to use clocked flip-flops configured as a one-shot, as shown in post #14.

 

Over the years, I have developed some circuits with CMOS 40103, 8 bit preset synchronous down counter.

The standard CMOS versions are not fast enough, but there are 74HC versions today.

Two pieces 74HC40103 should be able to handle the counter task fully synchronized, with a negative output signal corresponding to a single input clock pulse.

 

It seems like the best approach is to use clocked flip-flops configured as a one-shot, as shown in post #14.

Wally does not show the first decade of division. To keep the body count down, his first chip could be a dual decade counter since its output duty cycle does not affect the nature of the last 4017's outputs.

I don't remember if this came up in the first thread: If the TS can change the input clock to 10.24 MHz, then the counters can be a single 12-bit device. The output pulse would be 102.4 ns.

ak

 

Here is a sychronous solution.


The catch here is that the output is half the input clock period.
If you input a 5MHz clock, the output is 100ns at 5kHz.

You can get 100ns at 10kHz by preloading one of the counters to 5.

Edit: I forgot to change the part number to 74HC192.

 

The catch here is that the output is half the input clock period.

How does that happen?
Does it trigger on both the leading and trailing edge of the clock?
If so, then the output pulse width is determined by the duty-cycle of the 5 MHz clock.

 

How does that happen?
Does it trigger on both the leading and trailing edge of the clock?
If so, then the output pulse width is determined by the duty-cycle of the 5 MHz clock.

Correct. According to the datasheet, the CARRY OUT signal follows the low portion of the COUNT UP input pulse.

 

Here is a synchronous solution that outputs the required pulse, 100ns wide every 100μs.

 

Simulation of circuit in post #33...

Freq Out=9999.91Hz
PW=100.927ns

 

I'm trying to get the chip count down to 2 (not counting the 10 MHz clock).

1 - 74HC4040 12 bit counter - need 10 bits
1 - 74HC30 8-in NAND gate to decode 1000
1 - R-C differentiator to reset the counter

Or something like that.

ak

 

Depends on how accurate one wants the timing.
You can do it with one 555-timer chip and one 74LS123 chip.

 

ATTINY84 has a 16 bit PWM, and can take an external input, so / 1000 with
exact .1% duty cycle a breeze.

One chip, + 1 capacitor for bypass on its power pin.


Regards, Dana.

 

I think this meets all of the stated reqs, including no flash/no programming. The differentiator might need tuning. The counter does not have to be VHC; that's what is in my library. There are two possible issues: a) the output pulse is negative-true; b) the output occurs every 1001 counts.

The nice thing about ripple counters is that when decoding a unique number while up-counting, you don't have to decode the zeros. Outputs Q3-Q9 decode the value 1000d. They are stable with the first occurrance of 1000 (11 1110 1000h) as Q0 transitions from 0 to 1. Q0 is a 5 MHz signal, so its positive half-cycle is 100 ns. When it returns low, U2 pin 8 goes high and resets U1.

ak

Edit: There might be a way to have the output pulse at count 1000. Hmmm ...

 

Given the design in post #38 4040 is a ripple counter, asynchronous,
real tempting to run this thru a simulator for glitch evaluation. Especially
given the prop delays chip has and decoding gate.

Given you want such a controlled low duty cycle, narrow pulse width
output, do this with synch counters or pwm with sync core. Like most
processors have.

Regards, Dana.

 

The output pulse width is controlled by Q0 only; clock in > toggle FF > output driver. All of the other outputs are stable when Q0 goes from 0 to 1 and 1 to 0. Across three datasheets there is no mention of a prop delay difference in the 0-1 and 1-0 transitions.

The HC30 prop delay is listed as 12 ns typical at +25C. Again, there is no change in delay for the two transition directions, so this 12 ns delay is added to both edges of the output pulse. It and the ff delay show up as a phase delay, but *any* circuit or method has some kind of delay between the clock input and whatever the output is. In this case, the 100 ns output pulse width still is firmly bolted to the input clock period divided by two.

Note, this circuit might not work with synchronous counters; it assumes ripple counters for stability.

ak