1 bit counter using D-latch

Thread Starter

neugierige

Joined Nov 24, 2019
6
Hello,
I'm trying to simulate 1 bit counting operation by just logic gates.
I have connected Qnot(pin 4) to D(pin 6) and using switch left hand side to R1 resistor.
I want to reverse Q(pin 3) signal by every pulse generated by the switch (left hand side to R1 resistor).
But, it doesn't work.
d_latch.pngPlease let me know what I should additionally add to this circuit to avoid errors.
Thank you very much :)
 

djsfantasi

Joined Apr 11, 2010
5,958
Where’d you get that schematic and do you understand how it works? Is this schoolwork!

In general, counters are implemented using flip flops. Your one bit case you describe is just one type of flip flop. Once you recognize that, a quick Google search will give you your answer. You will be able to create a circuit with just NAND or NOR gates.
 

dl324

Joined Mar 30, 2015
9,606
Welcome to AAC!

Is this homework? If it is, please post the entire text of the problem.
I want to reverse Q(pin 3) signal by every pulse generated by the switch (left hand side to R1 resistor).
But, it doesn't work.
What position is the switch to the left of R2 in when you're trying to toggle the other one?
 

Thread Starter

neugierige

Joined Nov 24, 2019
6
Where’d you get that schematic and do you understand how it works? Is this schoolwork!

In general, counters are implemented using flip flops. Your one bit case you describe is just one type of flip flop. Once you recognize that, a quick Google search will give you your answer. You will be able to create a circuit with just NAND or NOR gates.
1574619447993.png
I wanted to understand how a 1 bit counter works and found the DTFF in proteus, then after some search I draw myself that schematic, but in that schematic it doesn't work when Q complement is connected to D, On the other hand it works When I use DTFF. So that's why? Does something lacks in that schmatic?
 

djsfantasi

Joined Apr 11, 2010
5,958
View attachment 192766
I wanted to understand how a 1 bit counter works and found the DTFF in proteus, then after some search I draw myself that schematic, but in that schematic it doesn't work when Q complement is connected to D, On the other hand it works When I use DTFF. So that's why? Does something lacks in that schmatic?
Once again, after I and dl324 have asked, is this schoolwork?

And what the heck is a DTFF? Don’t use acronyms that no one knows.
 

djsfantasi

Joined Apr 11, 2010
5,958
Sorry DTFF is D-type flip flop, and yes it's part of a school work.
Finally. What is the exact problem statement given you?

The rules on this forum treat schoolwork or homework questions differently. We aren’t allowed to give you a direct answer to your question but rather can only guide you in solution. On the other hand, there is a greater responsibility of the thread starter to post all work!

What have you done to analyze the schematic you presented? Show your work here.
 

Thread Starter

neugierige

Joined Nov 24, 2019
6
Actually they gave me a Digital Project called door lock with password,
at first I needed to read 4x4 keypad. So I had 4rows and 4 columns. To get which key is pressed I needed a counter that counts from 0 to 3 and I connected that signal to a 2to4 decoder to make only one column selected at a time. But I couldn't find 0to3 counter so I made one by searching internet and drawing this:1574622346663.png
from"https://www.quora.com/How-do-l-design-a-2-bit-up-down-counter-using-d-flip-flop"
As it seems Q-not is connected to D.
But after that, as I'm curious, I thought why I can't do that by just using simple logic gates like and,or,not, etc.
So I tried but it didn't work.

My project is bellow
1574622919217.png
At left most hand side, there is another decoder(4 to 16) which is just for verifying which button is pressed.
 

Attachments

djsfantasi

Joined Apr 11, 2010
5,958
And I’m in a mood where I think of something else after replying.

Before my next comment, what do you mean by “but, it doesn’t work”? How are you determining that it doesn’t work?

I repeat my question. What have you done to analyze the schematic (of the one bit counter) that you presented? Do you have a logic table, documenting the outputs for all possible inputs?
 

dl324

Joined Mar 30, 2015
9,606
As it seems Q-not is connected to D.
Do you know how to derive the equations for a mod 3 counter using D flip flops?
But after that, as I'm curious, I thought why I can't do that by just using simple logic gates like and,or,not, etc.
So I tried but it didn't work.
What didn't work? BTW, a latch isn't the same thing as a flip flop. D latches are level sensitive, D flip flops are edge triggered. Changes on the input don't affect the flip flop unless the input signal is stable for at least the input setup time.
 
Last edited:

djsfantasi

Joined Apr 11, 2010
5,958
Do you know how to derive the equations for a mod 3 counter using D flip flops?
Im confused... What does a mod 3 counter have to do with his problem?

What didn't work?
Good luck getting an answer. This has been asked before.

BTW, a latch isn't the same thing as a flip flop.
Where did latches enter the conversation? I reviewed the entire thread to see where they had been mentioned (I didn’t remember anyone saying something about a latch). And I didn’t find a reference other than your comment. Going off on a tangent isn’t going to help the TS.
 

Thread Starter

neugierige

Joined Nov 24, 2019
6
Sorry, I felt asleep.
What didn't work is the output signal(Q) couldn't be toggled by just changing position of the switch left to R1 resistor.
Because initial state of the Q is neither High nor Low.
After some effort I could do that:
1574663013054.png
Firstly I press to the BTN1 to avoid instability of Q and Q-not.
After that I change the position of SW1. Now Q-not is connected to D.
And lastly I can switch Q by just pressing to the BTN1.
But there is still a problem, this time output-Q changes instantaneously So when it's High it becomes Low and High again,
before I release BTN1.
Thanks to dl324 . Now I Know It works by edge triggering.
To perform edge triggering i tried this 1574663642091.png
and I set high-low delay of the first inverter to 16ms. Now looks like it works.

I have one more question: What should I do to avoid instability of Q and Q-not pins without using manual switch?
Sorry for my callowness.
Thanks a lot :)
 

dl324

Joined Mar 30, 2015
9,606
The first latch should have worked with the left switch opened.

I'm not going to analyze your second circuit. Your style isn't conducive to reading. You should learn to draw circuits in the "usual" topologies and avoid unnecessary wire jogs and scenic routing.
I have one more question: What should I do to avoid instability of Q and Q-not pins without using manual switch?
I didn't analyze the circuit, but my impression is that you've discovered the weakness of a latch. A master slave configuration is used to avoid the race condition and makes the circuit edge triggered.
 
Top