All About Circuits

Please help me :-(

T

tshuck

Joined Oct 18, 2012
3,534
This sounds like it's for a school project.

So, show us what you've done. Show us the flow chart you made in order to understand what you need to do. Then we will help you write it.
 
thatoneguy

thatoneguy

Joined Feb 19, 2009
6,359
Please post an image of your state machine which you would like to be realized in Verilog.

It's impossible to write code for a state machine that, from our point of view, does not exist.
 
A

Thread Starter

Abanah

Joined Jan 16, 2013
4
I have attached the architecture for your reference. Fault tolerant architectures.jpgI have to write verilog coding for fault tolerant architectures based on finite state machine. The functional unit is considered as full adder. Functional unit (FU) together with that checker acts as FSM. Need help as how to proceed and write codings for those architectures. Thanks in advance..Fault tolerant architectures.jpg
 
A

Thread Starter

Abanah

Joined Jan 16, 2013
4
In DUPLchck architecture, I have constructed a full adder using fsm which signifies the functional unit(FU) along with the checker. Two functional unit blocks are taken in which error is introduced in one functional unit,i.e. full adder. Both the outputs of FU are given as input to the multiplexer. MUX gives output if any one of FU is operating correctly. If there is an error it generates error output.
Full adder using FSM:
module fsm(cin,clk,s);
input cin,clk;
output reg s,cout;
reg [1:0]q;
initial
q=0;
always @(posedge clk)
begin
q[1]<=q[1]^q[0]^cin;
q[0]<=(q[1]&q[0])|(q[1]&cin)|(q[0]&cin);
s<=q[1];cout=q[0];
end
endmodule

In DUPLchckcmp , how the checker2 can be implemented.
 
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