Logic gate jitter causes
Today at 7:53pm
Hi all,

Looking for some thoughts on some persistent XOR gate output jitter I am experiencing. Taking a beating. The basics:

- quadrature square waves @ ~34kHz from a 2-circuit PPOP comparator IC are driving the PPOP XOR gate inputs
- little/no deterministic jitter is seen in these 2 outputs / inputs to the XOR gate (distribution of HI and LOW pulse widths and period are approximately Gaussian with low variance)
- very clear jitter seen on XOR gate output (2 very distinct clusters in histogram of LOW pulse widths; HI pulse widths are Gaussian with small variance)
- No amount of supply bypassing on either the XOR or the comparator circuit would so much as affect the jitter
- the XOR gate output edge whose phase jitters is the LOW-HIGH transition. At the time of this edge, one of the quadrature square waves is also transitioning either H-L or L-H.
--- the shorter of the two low pulse widths happens when the one quadrature square wave is also transitioning L-H, and the longer of the two low pulse widths happens when the input is transitioning H-L. Assuming the issue is VCC or GND movement and the true switching threshold occurs at a fixed point between the VCC and GND as seen at the device, this would make sense. However, the lack of effect of supply bypassing puts a hole in this theory.

What are the odds that what I'm seeing is layout related / direct electromagnetic coupling between the traces rather than VCC / GND bounce? If this is the case are there any techniques I could try before waiting for a layout revision?

Thanks in advance for thoughts / advise.

 

Logic gate jitter causes
Today at 7:53pm
Hi all,

Looking for some thoughts on some persistent XOR gate output jitter I am experiencing. Taking a beating. The basics:

- quadrature square waves @ ~34kHz from a 2-circuit PPOP comparator IC are driving the PPOP XOR gate inputs
- little/no deterministic jitter is seen in these 2 outputs / inputs to the XOR gate (distribution of HI and LOW pulse widths and period are approximately Gaussian with low variance)
- very clear jitter seen on XOR gate output (2 very distinct clusters in histogram of LOW pulse widths; HI pulse widths are Gaussian with small variance)
- No amount of supply bypassing on either the XOR or the comparator circuit would so much as affect the jitter
- the XOR gate output edge whose phase jitters is the LOW-HIGH transition. At the time of this edge, one of the quadrature square waves is also transitioning either H-L or L-H.
--- the shorter of the two low pulse widths happens when the one quadrature square wave is also transitioning L-H, and the longer of the two low pulse widths happens when the input is transitioning H-L. Assuming the issue is VCC or GND movement and the true switching threshold occurs at a fixed point between the VCC and GND as seen at the device, this would make sense. However, the lack of effect of supply bypassing puts a hole in this theory.

What are the odds that what I'm seeing is layout related / direct electromagnetic coupling between the traces rather than VCC / GND bounce? If this is the case are there any techniques I could try before waiting for a layout revision?

Thanks in advance for thoughts / advise.

Is it possible to connect a resistor (or higher value resistor) in series with the outputs of your XOR. The current high load is causing power supply ripple and glitching the inputs.

Post a schematic and pcb layout.

 

http://www.ti.com/lit/ds/symlink/lmv761.pdf
This is a link to a TI datasheet for a comparator IC. Take a look at section 7.2.3, Hysteresis. This may be the cause of your jitter.

 

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Is it possible to connect a resistor (or higher value resistor) in series with the outputs of your XOR. The current high load is causing power supply ripple and glitching the inputs.

Post a schematic and pcb layout.

Thanks, I will try this. I do actually have a pad for this on the PCB. Will post layout and schematic if it doesn't work.

The thing is that the XOR gate output is simply driving a switch control input which is very high impedance at least at DC. They don't specify the input capacitance so I'm not sure what the AC impedance that the switch edge would see is, but you might be right it may be fairly low.

 

http://www.ti.com/lit/ds/symlink/lmv761.pdf
This is a link to a TI datasheet for a comparator IC. Take a look at section 7.2.3, Hysteresis. This may be the cause of your jitter.

Unfortunately there is no such discussion of hysteresis in datasheet of the XOR gate I'm using, so I don't know what the hysteresis specifications are. The comparator outputs themselves are clean and jitter free.

 

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Push pull output sorry

 

Unfortunately there is no such discussion of hysteresis in datasheet of the XOR gate I'm using, so I don't know what the hysteresis specifications are.

In standard logic gate families, there are no XOR or XNOR gates with hysteresis.

This is a link to a TI datasheet for a comparator IC. Take a look at section 7.2.3, Hysteresis. This may be the cause of your jitter.

By itself, the 761 has no hysteresis. The circuit in the datasheet uses standard positive feedback to add this function.

Schematic?

ak