Worth Using Alternative to 555 for Astable Clock

Thread Starter

devereaux

Joined Jan 21, 2019
3
I'm building an 8-bit computer, inspired by Ben Eater's video series but based on the 6502 instruction set, and using 74HC logic. I'd originally planned to use all breadboards like he did but might instead design the modules as PCBs. That aside, I've been thinking about the clock generation. My design will use only one 64Kbit parallel EEPROM for the microcode, requiring its own clock for sequentially pulling out 4 bytes to make the full 32-bit control word. Other designs I've seen use up to 4 EEPROMs but that's not appealing to me as a design. For reference the least significant 8 bits of the EEPROM's address will be the instruction opcode, the next 3 bits the timing and most significant 2 bits the address offsets for the control word segments. In order to do this I need a clock that will run at least four cycles within the low time of my master clock, since the control logic is triggered when the master clock goes from high-to-low.

So, say my master clock runs at 10KHz, and ideally has a 50% duty cycle, the low time will be 50μs. My EEPROM read clock will therefore need to be around 100KHz to comfortably complete its four cycles before the master clock goes high again, since its period is 10μs. I'm not bothered about running the master clock that fast TBH as it's all for learning purposes.

Ben Eater and the other projects I've seen based on his all use 555 timer chips for their clocks. I know I can comfortably generate 10KHz using a NA555 timer circuit in astable mode but doing my research I've seen people describing the 555 as a dinosaur, with better solutions available. However what, in your opinions are the best solutions?

Here are my requirements for the clock module:
- Slow mode - adjustable using a pot for running anywhere between 1Hz and up
- Fast mode - fixed frequency, e.g. 10KHz.
- Manual mode - debounced switch for stepping through instructions.

The Schmitt Trigger inverter method looks interesting, however I don't yet have a 74HC14 to test with, and have been considering the TLC555 (a more up-to date LinCMOS chip, whatever that is...) as this can operate at frequencies up to 2MHz. From my basic understanding the Schmitt Trigger method results in a 50% duty cycle using just one cap and one resistor.

Happy to still use a 555 for debouncing the switch for manual mode, but can look for alternatives.

I'm not interested in using crystals as these tend to work at much higher frequencies than I need, and I'm not bothered if the timing has some degree of tolerance, as long as it's within 10% of my target speed.

Thoughts? I'm a mostly-newbie, having rediscovered electronics 25 years after I last made circuits at school, so any and all useful info gratefully received!

Thanks!
 

dl324

Joined Mar 30, 2015
16,846
Ben Eater and the other projects I've seen based on his all use 555 timer chips for their clocks. I know I can comfortably generate 10KHz using a NA555 timer circuit in astable mode but doing my research I've seen people describing the 555 as a dinosaur, with better solutions available. However what, in your opinions are the best solutions?
Who cares how old the design is? It's not like it's been obsoleted and difficult to find.
 

Thread Starter

devereaux

Joined Jan 21, 2019
3
Thanks all.

I was just curious as to what might function as an alternative, but as you've said the 555 is a fine timer (and if it ain't broke...).

Are you concerned that the two clocks will lose their synchronization? Why not divide the eeprom clock by 4 and use that to clock your control logic?
Interesting idea. I'd not really thought about that. As long as the four cycles can comfortably fit within one of the master clock's low period it shouldn't be a problem.
 

MrChips

Joined Oct 2, 2009
30,720
Use a 555-timer and divide it down to get your four phases.
Use a CMOS 555-timer. You can select the resistor values to obtain close to 50% duty cycle with no additional components necessary.
 

djsfantasi

Joined Apr 11, 2010
9,156
Interesting idea. I'd not really thought about that. As long as the four cycles can comfortably fit within one of the master clock's low period it shouldn't be a problem.
Consider this simplified scenario. Your eeprom clock runs at 4 something (Hz, KHz, MHz... while the units will matter in real life, it doesn't matter to my example). If the master clock runs at 1 something, you can fit four eeprom cycles into one cycle of the master clock. But what if your eeprom clock drifts 10%? Then after 10 cycles of the master clock, you will lose data. Maybe earlier, but after 10 cycles, you will be off one whole cycle of the eeprom clock.

Maybe both clocks drift. Maybe you’ll be luck. Maybe it will be worse.

Depends on your definition of comfortably fit, as well. Maybe you run the eeprom clock at 8 something and discard half the cycles.

As long as you aware of the possibility for losing synchronization. Or you can do as MrChips and I have suggested and divide down the eeprom clock to get the waveform for your magic clock.

One additional thought. I’m not sure how important is the 50% duty cycle. To guarantee it, instead of divide by four, divide by 8. Use this output for you slower logic click and use the divide by 2 output for your eeprom clock.
 
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