with gates do they all wire together?

Discussion in 'Digital Circuit Design' started by traymond, Oct 28, 2017.

  1. traymond

    Thread Starter New Member

    Oct 28, 2017
    Concerning like for instance
    gates, like AND and then NAND gate do these usually have wires joining both AND and NAND gates or do these gates
    ALWAYS not ever wire together.
    I have seen graphical images of older LS logic gates and it seems these work by themselves and independent from the other

    Im currently intrested in an older CMOS chip layout (very simple) and wondering if the above is always true.

    BTW on this forum is it okay to paste in like JPG images and post these or is this forbidden on this forum?

    Well the chip Im figuring out is an older CMOS gate level controller (very simple design) Im tinkering with that is. :)

    I know this is a silly question but something that I have noticed with older MOS chips, as far as the gates.
    I know ONE SINGLE gate has ITS wires but the different gates Im unaware if they INTERCONNECT in the IC circuit?

  2. bertus


    Apr 5, 2008

    You can upload files and images using the "upload a file" button

    The popup will show you wich fileformats are allowed

  3. andrewmm

    Active Member

    Feb 25, 2011
    Gates are a great way to learn,

    one word of caution, you mention the cmos gates,
    they have a few fobels, such as dying at the first sign of static

    The old '74' series of LS logic is still around , and come s in nice 14 / 16 pin 0.3 inch wide packages that pne can see, and a lot more resilient to abuse,
  4. WBahn


    Mar 31, 2012
    You need to be a lot more specific about what you mean by "wired together".

    In general, each node (the common wired connection shared by two or more component connections) need one driver (such as the output of a logic gate) and some maximum number of inputs to logic gates. The maximum number of inputs that an output can drive reliably is called the fanout of the driving gate. There are some exceptions to this rule, particularly with open-collector (open-drain) and three-state outputs, but worry about those when you get to them.