I am using the STUB4500 USB c PD management chip.
Schematic below shows how I'm implementing it. I guess the 100k to 22k divider is to keep Vgs below 20v when the chip pulls vbus_en_sync to 0. With vbus at 20v, the Vgs of T1 will be about 3.6 volt.
Can I increase R11 to say 44k and make Vgs ~6v in hopes of getting a lower rds on? Will that slow down the turn on time for T1? Is it already too slow?

Schematic below shows how I'm implementing it. I guess the 100k to 22k divider is to keep Vgs below 20v when the chip pulls vbus_en_sync to 0. With vbus at 20v, the Vgs of T1 will be about 3.6 volt.
Can I increase R11 to say 44k and make Vgs ~6v in hopes of getting a lower rds on? Will that slow down the turn on time for T1? Is it already too slow?
