Dear all,

I am building a CPU from scratch using logic gates and I have a puzzle that has just come to mind.

I have planned the RAM write cycles in the following way:

If the CPU wants to write data to RAM, it will spread the writing in 2 cycles. At the beginning of the first cycle/state/positive clock edge, the CPU will output the address it needs to write to into the Address bus. It will also output a control signal to tell the RAM chip that it should be writing data. This signal however will not be read by the RAM instantly, it will take half a clock cycle, because this signal will be first sent to a D flip flop, and latched at the downward clock edge.

Then, at the next clock cycle/state/positive edge, the CPU will send a RAMEnable signal so that the RAM will be working, it will also output the data to be written on the data lines. Here's my problem:

At the beginning of this second cycle, the CPU will also need to output the address on the address lines, because otherwise RAM will receive an incorrect address for half a clock cycle and that's not good. The way I send the address to the bus is through a multiplexor, which selects what register will be sending its "data", in this case an address, to the bus. The way this address is sent to the address bus is through a multiplexor that selects which register will be used as an address base. At the first writing cycle, the CPU outputs 2 control bits, which are sent to the multiplexor to select the register.

My problem is that at the second cycle, since I will also be needing to output the address, when the CPU is changing states and entering cycle 2, I am afraid that the 2 control bits that are sent to the plexor will "wobble" for a few nanoseconds before it settles again to the correct value.

Do you see what I mean? Because there is some combinational logic that decides what control bits will be output at each CPU state, when the values fed into this logic are changed, the outputs will wobble for a few nanoseconds until they settle again. But I will be using the values while they wobble because the Address Source bits are used by the RAM from cycle 1 to cycle 2.

My question is, if this value wobbles for a few nanoseconds, and the address wobbles for a few nanoseconds, will the RAM overwrite a random address, or will the RAM not notice this because there is a minimum amount of time that an address needs to be stable in order for the RAM to recognize it and use it to write data at that address?

The wobble should be very short. My question is, will the RAM recognize the address no matter how short the time it stays on, or not?

Your help is immensely appreciated !!

Thank you

Paul

 

Look at the setup and hold times in the datasheet for the RAM you're using.

 

You don't want any glitches in the control lines. After the address (and data for a write) have come up and are stable only then do you want to toggle the control lines, and toggle them cleanly while observing all the required set up and hold times.

This may mean you need to latch the control lines as you latch the address.

Further assistance would require you to disclose the mystery memory chips you use.

 

Hi Paulo!

The RAM you will be using should be controlled in the following manner:

1. Step 1 - Setup address, data lines and CE
2. Step 2 - Either toggle WE to write or keep OE low to read

Address and data lines need to be stable before writing to the RAM chip and writes occur on the falling edge of WE. For reading, you can just keep OE low and as you cycle through the addresses the data appears on the RAMs databus.

All the best,
Robin

 

Dear all,

I am building a CPU from scratch using logic gates and I have a puzzle that has just come to mind.

I have planned the RAM write cycles in the following way:

If the CPU wants to write data to RAM, it will spread the writing in 2 cycles. At the beginning of the first cycle/state/positive clock edge, the CPU will output the address it needs to write to into the Address bus. It will also output a control signal to tell the RAM chip that it should be writing data. This signal however will not be read by the RAM instantly, it will take half a clock cycle, because this signal will be first sent to a D flip flop, and latched at the downward clock edge.

Then, at the next clock cycle/state/positive edge, the CPU will send a RAMEnable signal so that the RAM will be working, it will also output the data to be written on the data lines. Here's my problem:

At the beginning of this second cycle, the CPU will also need to output the address on the address lines, because otherwise RAM will receive an incorrect address for half a clock cycle and that's not good. The way I send the address to the bus is through a multiplexor, which selects what register will be sending its "data", in this case an address, to the bus. The way this address is sent to the address bus is through a multiplexor that selects which register will be used as an address base. At the first writing cycle, the CPU outputs 2 control bits, which are sent to the multiplexor to select the register.

My problem is that at the second cycle, since I will also be needing to output the address, when the CPU is changing states and entering cycle 2, I am afraid that the 2 control bits that are sent to the plexor will "wobble" for a few nanoseconds before it settles again to the correct value.

Do you see what I mean? Because there is some combinational logic that decides what control bits will be output at each CPU state, when the values fed into this logic are changed, the outputs will wobble for a few nanoseconds until they settle again. But I will be using the values while they wobble because the Address Source bits are used by the RAM from cycle 1 to cycle 2.

My question is, if this value wobbles for a few nanoseconds, and the address wobbles for a few nanoseconds, will the RAM overwrite a random address, or will the RAM not notice this because there is a minimum amount of time that an address needs to be stable in order for the RAM to recognize it and use it to write data at that address?

The wobble should be very short. My question is, will the RAM recognize the address no matter how short the time it stays on, or not?

Your help is immensely appreciated !!

Thank you

Paul

How fast is your RAM? How fast is your clock cycle? Bless you for having the wherewithal to even think about such things. The speed of the ALU always slowed me up. Personally, I always thought a Harvard architecture RISC design would be better than this x86 garbage. Or programmable microcode CISC would let people create their own custom instructions.

 

Hi Paulo!

The RAM you will be using should be controlled in the following manner:

1. Step 1 - Setup address, data lines and CE
2. Step 2 - Either toggle WE to write or keep OE low to read

Address and data lines need to be stable before writing to the RAM chip and writes occur on the falling edge of WE. For reading, you can just keep OE low and as you cycle through the addresses the data appears on the RAMs databus.

All the best,
Robin

Thanks Robin,

I actually know this, but my problem is exactly this.

Because I am using the address during two cycles, if I active WE on the second cycle at the same time as my CPU state changes and hence the AddressSource plexor wobbles, I can't be sure if I will be writing to the right address.

The address is surely correct on the first cycle, but the problem is when changing from the first cycle into the second, because the control lines will al wobble.

You see the problem?

I think the solution must be to latch the address before using it on the RAM. If I use one cycle to latch the address, then it will be constant during the first and second cycles. For this I will use a register I will name Memory Address Register, and I think this is done in many CPU's.


This issue is very subtle. The problem arises because the control lines need time to settle, and will wobble in between changing CPU states.

You said the RAM writes on the falling edge of WE, but actually, it also writes when the address changes. I have tested this with my ram. If WE is active and constant, and the address changes, the ram will write on all addresses in between!

And this is the problem, because as I change states, my address plexors will wobble and change the address line while WE is low!

 

How fast is your RAM? How fast is your clock cycle? Bless you for having the wherewithal to even think about such things. The speed of the ALU always slowed me up. Personally, I always thought a Harvard architecture RISC design would be better than this x86 garbage. Or programmable microcode CISC would let people create their own custom instructions.

Thank you sir that's very nice of you.

The RAM is 70ns write cycle. I worry but if the address changes for 35ns for example, will the RAM write half the data on the first address and half on the second? Or will the RAM skip the 30ns address? God knows!

I think to be on the safe side the address must be latched while the ram uses it.

 

Here is a link to the datasheet: http://www112.zippyshare.com/v/R3tB9Ldt/file.html

I think that even if it shows that the setup to write end time is 60ns, that doesn't prove that keeping an address for say 10ns won't make the RAM write data to this ephemeral address, or does it?

Would the RAM ignore any address that stays on for less than 60ns ?

 

@PauloConstantino
From what you describe you need to latch the address and data lines. You cant have "wobbles" which occur on ripple counters because SRAM is fast compared to your discrete CPU. Even then its just good practice

Best of luck!

 

@PauloConstantino
From what you describe you need to latch the address and data lines. You cant have "wobbles" which occur on ripple counters because SRAM is fast compared to your discrete CPU. Even then its just good practice

Best of luck!

Well what I described is what I had described on my first post!

 

Here is a link to the datasheet: http://www112.zippyshare.com/v/R3tB9Ldt/file.html

Zippieshare? Nah, not gonna download from there.

Would you Just upload your file here, or link to the manufacturers page?

 

Zippieshare? Nah, not gonna download from there.

Would you Just upload your file here, or link to the manufacturers page?

OK don't download.

 

OK don't download.

Chump don' want no help, chump don't GET da help!