Why we need Read bit in SPI and what is a dummy byte ?

Thread Starter

Xenon02

Joined Feb 24, 2021
504
SPI technically be be any size (SPI allows word sizes of several bits, not necessarily rounded up to a multiple of 8, I've seen and used devices with odd-ball bits) but usually it's from 8 to 32-bits physical for each shift register. Most 32-bit processors allow for physical register byte sizes up to 32-bit to optimize transfers.
A so it can also have an odd size as well. Good to know.


So this slave works in 8 bit format ? And has 32 bits as I understand ?

I also asked to say if my points are :


- Is it also device dependant how the SPI with 16 bit registers interprets its data ? It works in 8 bit format so my 1st proposition to how it could work is that first 8 bits are for transfer only and next 8 bits of the registeris for receive only and that's how it works for 8 bit format. Not a bad conclusion?

- If the SPI with 16 bit register works as 16 bit format and not 8 bit format, means that is must send 16 bits and receive 16 bit ? If so then Slave register must also have 16 bit to work in 16 bit format. That's what I thought of.

- If SPI works in 16 bit format then if Slave is in 8 bit format (want to receive 1 byte or 3 byte) it wouldn't work. So Slave must be also in 16 bit format.

- The size of registers can tell how maximally can be the format of SPI.

Please if it's possible tell in every point if they are okey/partly ok or completelly wrong. I want to know what I am standing on.
If it's possible :>
Wanted to know if I understand it or atleast do I start correctly.
 

Thread Starter

Xenon02

Joined Feb 24, 2021
504
SPI technically be be any size (SPI allows word sizes of several bits, not necessarily rounded up to a multiple of 8, I've seen and used devices with odd-ball bits) but usually it's from 8 to 32-bits physical for each shift register. Most 32-bit processors allow for physical register byte sizes up to 32-bit to optimize transfers.
https://ww1.microchip.com/downloads/en/DeviceDoc/61106G.pdf
So I can assume that these points :


- Is it also device dependant how the SPI with 16 bit registers interprets its data ? It works in 8 bit format so my 1st proposition to how it could work is that first 8 bits are for transfer only and next 8 bits of the registeris for receive only and that's how it works for 8 bit format. Not a bad conclusion?

- If the SPI with 16 bit register works as 16 bit format and not 8 bit format, means that is must send 16 bits and receive 16 bit ? If so then Slave register must also have 16 bit to work in 16 bit format. That's what I thought of.

- If SPI works in 16 bit format then if Slave is in 8 bit format (want to receive 1 byte or 3 byte) it wouldn't work. So Slave must be also in 16 bit format.

- The size of registers can tell how maximally can be the format of SPI.
Are all correct ? With the additional info that the SPI registers can have odd size not only the multiplye of 8 ?
Because I don't know if my points were correct that's why I also asked if it's possible to say in each of my points (4 in total) if they are correct/partly correct or totally wrong :D

Thanks and have a nice day :>
 
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