I have a question about the well-know limitation of Eagle (I'm using version 7.3.0): merging two nets with two different names. This problem arises usually when trying to connect two intentionally separated ground planes.

After googling a lot I discovered that the workaround available are essentially two:

1. create your own two-pin device where pins (pad or smd) are overlapping (and approve the related DRC errors);
   
2. add an additional foo-pin to your IC footprint and connect it to the VSS/GND by a strip of overlapping copper (again you have to approve the related DRC errors)

My question is: why I cannot simply manually route two traces, departing from the pads that I want connect to, and make them encountering in one point with a little overlap? In this way I have not to create a foo device and/or modify the footprint of my device (yes, I still have to approve a DRC error).

There is a reason why nobody proposed a similar solution?
It's just to have some kind of consistency between the PCB layout and the schematics?

 

If you merge the two grounds and they have (or will have) ground pour, then the pour will include both grounds. I have always separated grounds with KEEPOUT areas that separated the different ground area pours (even though they were the same ground).

You will always have this problem if the grounds are eventually connected at any point, like for a power connection. You can do what your question asks, but the DRC errors might overwhelm you. It is never a good idea to skip a DRC check because of the problems that it might find. If you lay out your board with the KEEPOUT areas set where you want them, then you can safely connect the two grounds together and the DRC will not pop an error.

It is important to always keep consistency between schematic and layout.

 

If you lay out your board with the KEEPOUT areas set where you want them, then you can safely connect the two grounds together and the DRC will not pop an error.

Do you mean that you use a common GND net and then you add a KEEPOUT layer to give the ground plane the desired shape? I mean... do you "draw" an isolating "channel" around your internal ground plane until you obtain the shape you want (leaving a small area where the internal GND plane actually connect to the surrounding general plane)?

I have a problem drawing a KEEPOUT polygon: it has no effect when I push the RATSNET button, it is ignored. The only layer having some effect is the tRESTRICT, maybe you mean that layer?

 

SLK001, do you mean something like that?




In the example above there is only one GND net for every pin. The guard-ring plane is created by shaping his outline with two tRESTRICT polygons.
When pressing the RATSNEST button the common ground plane "flood" the ring (when done, you simply delete tRESTRICT polygons).

 

Maybe the same result can be achieved by drawing a fat wire around the oscillator (combining it with a tRestric polygon)?
I get zero DRC error in this case too (after removing the tRestric polygon), it looks not fine but seems to work...

 

Yeah, it is tRESTRICT that I am talking about. You don't have to use polygons on tRESTRICT - a line will work fine (you can define the isolation in the polygon INFO menu).

Do NOT remove the tRESTRICT lines after you run DRC. IIRC, when you create GERBER files, RATSNEST will be run again and your nets will be run together once again. At this time, you may NOT catch the error.

 

Ok.
Thanks for the trick about generating GERBER file!

 

I also recommend that you turn OFF thermals. If you look at the GND connections on the flooded pic in #4, you'll see that it barely connects. This creates a relatively high impedance ground that can cause problems that are almost impossible to find the cause. The higher the frequency that you operate, the more effect the high impedance ground has on circuit operation. I used to design RF power transmitter circuits for radio boards in the 800 MHz region and ALL of my grounds were flooded. The production people screamed bloody murder about this, but I was able to provide concrete evidence that poor grounding had a detrimental effect on my designs. It was a fun meeting - the Vice President of Manufacturing and every boss down to the lowliest production line boss versus me and my manager. They pissed and moaned for about an hour, then I got up and spoke for about 5 minutes, presenting all my data. I walked out a winner on all points and the grounds remained flooded.

 

They pissed and moaned for about an hour, then I got up and spoke for about 5 minutes, presenting all my data. I walked out a winner on all points and the grounds remained flooded.

Epic!

 

Late to this thread; two thoughts from six layout packages over 30 years:

Most layout programs let you edit the thermal spoke width to adjust the copper-to-space ratio around the pad. I've never known why the default spoke width always is so thin, but since it is adjustable I don't care.

Separate from that, I don't understand the question. Of all the things that can go wrong when laying out a board, inadvertently connecting two different nets is the grand poobah of errors. Design-rule checking is not a bug, and not merely a feature - it is the program's raison d'etre. If two things (components, planes, whatever) are to be connected on the board, connect them on the schematic and push that to the netlist. Do you really want two ground planes connected with no supporting documentation?

ak

 

Yeah, it is tRESTRICT that I am talking about. You don't have to use polygons on tRESTRICT - a line will work fine (you can define the isolation in the polygon INFO menu).

Easy and niceeeeee!



General ground polygon: thermal off, isolate 16 MIL, name = "GND", layer = TOP
Restrict wire: width = 0, layer = tRestrict
Cutout polygon: width = 0, layer = TOP, pour = cutout
DRC errors: zero

 

Separate from that, I don't understand the question.

Simply, I was impressed by the number of people suggesting to create foo eagle-parts to join two separated ground planes.
I saw almost everything: overlapping pads, overlapping smd pads, smd pads with zero-clearance, strips of pour linking two pads, etc. etc
Since you have to manually approve inevitable DRC errors 'caused by the proposed "solutions", I thought "why don't simply overlap two traces to join two nets?"

As SLK001 explained, you don't really need separated grounds plane (and separated nets) in the schematic. You just need to exploit standard tools provided by Eagle to separate planes geometrically (in the layout editor) but not logically (in the schematic editor).

Now I'm pretty sure that you can do almost everything about ground planes by combining cutout polygons, t/bRestrict wires/polygons and fantasy.

 

Most of my designs were battery powered and contained both digital and sensitive RF circuits. Everything was powered by the battery and its return (ground), so the grounds were always connected - somewhere. No layout package knows to keep digital and RF circuit grounds separate, especially since they are the same net (I am familiar with Mentor and Cadence schematic capture and PCB layout tools). If you wanted to keep the digital noise out of the RF circuitry, then judicious routing of the ground was mandatory. Eagle accomplishes the ground dilemma with the ability to restrict ground pours. Sometimes you have to use separate ground pours to accomplish your objectives, such as when a trace must go from one area to another (if you cross a tRESTRICT line, you will get a DRC error). All restricted areas on inner layers must be with multiple polygon pours (there still isn't a RESTRICT option for inner layers).