I built a hex to 7-segment decoder using AND and OR gates -- well, actually I didn't finish it, but the 'a' segment works perfectly. Then I skipped ahead and built it (not hex though) using a 74LS47 (actually used a 74LS247 so I could get the tails on the 6's and 9's). Then I added a counter using D-type flip flops (74LS74).

Now, in reading various sources, trying to figure out how to get it to count from 0-9 only, skipping the garbage bits from 0b1010-0b1111 -- I came across this informative article: https://www.electronics-tutorials.ws/counter/count_2.html

They are using J-K flip flops (and I may have missed a page where they describe a T-type or Toggle flip flop). So I guess the difference between theirs and mine, is whether it switches on the rising edge or falling edge of the clock pulse.

Anyway, I wired mine like theirs, using the NAND gate on Q3 and Q0 (0b1001, 9), but then mine is a divide by 9 counter (resets from 8 to 0), instead of a divide by 10 counter (reset from 9 to 0)

My schematic (attached ) shows attaching the NAND gate to Q3 and Q0, but my breadboard (which you'll probably never be able to discern) is actually wired to Q3 and Q1 (0b1010, 10), in order to get it to work properly.

Why is that? Is it the rising/falling edge difference? Do I need to go back and re-read about the T-type flip flop? I'm not sure I'm fully understanding the difference. My clock module (not shown), has a manual pulse setting, and when I press and hold the button, the number increments, and nothing additional happens when I let go (so I assume its being triggered on the rising edge).

 

It's doing exactly what you are telling it to do.

What happens when the state is 8 (0b1000) and the clock rises?

The counter progresses to 9 (0b1001) and since all three inputs to your NAND gate are HI, the output goes LO resetting all of the flip flops to 0.

So your counter DOES go to 9, but it resets to 0 just a few nanoseconds later.

This is one of the big problems with using asynchronous logic (as soon as you use the asynchronous set/clear inputs as part of your normal logic, your design is now an asynchronous one).

 

They are using J-K flip flops (and I may have missed a page where they describe a T-type or Toggle flip flop). So I guess the difference between theirs and mine, is whether it switches on the rising edge or falling edge of the clock pulse.

Not necessarily.
Whether the FF toggles on the rising or falling clock edge is determined by the FF internal design, not whether it's a J-K or D FF.

My schematic
shows attaching the NAND gate to Q3 and Q0, but my breadboard (which you'll probably never be able to discern) is actually wired to Q3 and Q1 (0b1010, 10), in order to get it to work properly.
Why is that? Is it the rising/falling edge difference? Do I need to go back and re-read about the T-type flip flop?

Nothing to do with T-FFs. It has to do with how the counters reset.

You are not realizing that the flip-flops asynchronously (immediately) reset to zero at the start of the last count, thus it will be a divide-by-nine counter if the gate is connected to count 10 (which you found).
In other words, count 10 immediately resets to count 0 on the rising edge of the clock pulse (the end of count 9), so there are 9 clock pulses between count 0 and count 10.
Make sense?

Incidentally, I see no particular reason to add the clock pulse to the NAND gate input.

 

In general, clearing a counter or shift register by gating its own outputs is bad practice. Your circuit will generate a very narrow pulse on reset. The pulse will end as soon as any one of the flip-flops that are gated to produce reset is cleared (must also consider propagation delay of the gate). This may or may not meet the minimum required assertion time for the reset signal, so it may not reset all of the flip flops. The more flip flops involved, the more likely it is that there will be problems.

 

Not necessarily.
Whether the FF toggles on the rising or falling clock edge is determined by the FF internal design, not whether it's a J-K or D FF.
Nothing to do with T-FFs. It has to do with how the counters reset.

You are not realizing that the flip-flops asynchronously (immediately) reset to zero at the start of the last count, thus it will be a divide-by-nine counter if the gate is connected to count 10 (which you found).
In other words, count 10 immediately resets to count 0 on the rising edge of the clock pulse (the end of count 9), so there are 9 clock pulses between count 0 and count 10.
Make sense?

The "divide-by-N" value isn't dictated by how many clock clock pulses there are between 0 and 10, it's how many clock pulses there are between one occurrence of a particular event and the next occurrence of that same event -- in other words the period of the sequence.

If the counter goes from 0 to 10 but resets immediately without a clock pulse, then there the period is 10 clock pulses long and it is a divide-by-10 counter.

Incidentally, I see no particular reason to add the clock pulse to the NAND gate input.

There isn't a reason, other than it is common for people to try to incorporate the clock into their ad-hoc asynchronous logic design thinking that they've somehow now may it nice and synchronous. But all they usually accomplish is to make part of their circuitry use a gated-clock, which is usually bad ju-ju.

Another thing that is almost always overlooked is the possibility that during the transient between stable states that the counter outputs might briefly match the tested condition and trigger the reset. In ripple counters such as this it's pretty easy to verify whether this is possible (and if it is possible, then it almost certainly will happen since the transients in ripple counters are pretty deterministic).

 

The [edit] tutorial (why the heck did I type TI?) circuit is different.
The flip flops used trigger on the falling edge. By including the clock in the gating, the reset pulse does not begin until the rising edge of the clock after the falling edge. But their circuit is still wrong! It shows a reset pulse that lasts a full clock cycle and it cannot, by virtue of the fact that, all other things ignored, if can only be asserted (low) when the clock is high and it still suffers from the fact it ends one gate delay after the first flip-flop reset has propagate to its output.

I vaguely recall that the LS73 is a true edge triggered part, but I'm not sure. The standard TTL 7473 was in fact a "level triggered" JK flip-flop which made the transition on the falling edge of the clock, but could "opposite state catch" during the clock high time.

For comparison, look at the 74xx90 which is a true synchronous state machine.

 

In general, clearing a counter or shift register by gating its own outputs is bad practice. Your circuit will generate a very narrow pulse on reset. The pulse will end as soon as any one of the flip-flops that are gated to produce reset is cleared (must also consider propagation delay of the gate). This may or may not meet the minimum required assertion time for the reset signal, so it may not reset all of the flip flops. The more flip flops involved, the more likely it is that there will be problems.

Completely agree. If someone must use this kind of approach (and there are situations where asynchronous logic is fully justified) then every aspect of the design must undergo a LOT more careful consideration. One way to deal with this problem is to latch the reset signal upon detecting the triggering condition and then unlatching it only after the reset has been complete. That could be done by resetting that latch whenever the outputs are all zero. Another way to do it is to be willing to assume that half a clock cycle is sufficient and clear the latch when the clock is LO. But even here you have a critical race condition between the clock at this latch going HI and the trigger signal setting the latch -- but this is one that is pretty easy to ensure that the race is won in your favor (in fact, it would be very difficult to not win it).

 

somewhat off-topic

Are people actually still playing with LS? If so, I should put some more effort into trying to find a school that would like a gift of several hundred "new old stock" LS parts I'd really like to get rid of. Got a few spiffy "F" series parts, too, including some FIFOs.

 

If the counter goes from 0 to 10 but resets immediately without a clock pulse

What do you mean, resets without a clock pulse?
That's not the case here. It resets on the edge of the count of 10 clock pulse which makes it a divide by nine couner.

 

ok, I think I'm even more confused now -- I'm not sure if you guys agree or disagree with each other...

so, I'm looking at the datasheets for the 74LS90 (asynchronous?) and 74LS191 (synchronous), and it looks to me like they are gating the outputs of the flip flops internally, so I'm not sure I understand the difference, why it would be bad practice in my example using basic flip-flops (It sounds like I'm essentially building a 74LS90 from two 74LS76's and a 74LS00). I'm sure there are differences that I'm not seeing yet.

The fact that I have 10 items, and 9 intervals between them always confuses me. I'm always off-by-one, one way or another, until I draw it out on paper and actually count them. I expect the completed circuit to display each of the 10 digits a perceivable identical amount of time (displaying an eleventh digit for a few nano seconds when resetting to zero, is probably not perceivable enough to worry about - yet). So I still don't understand why the tutorial example advertises as a "divide-by-ten" counter, when it only counts from 0-8 (9 complete cycles, not 10). Did they simply make a mistake? Ah, maybe they did..., here's different example, and they used Q3 and Q1: https://www.ee.usyd.edu.au/tutorials/digital_tutorial/part2/counter03.html

I also don't understand why the clock is tied into the NAND gate either. Since you guys mentioned it, I disconnected mine, and I don't yet notice any degradation. Off the top of my head, it seems like the flip-flops will have their value for the full clock cycle, and by NAND'ing it with the clock pulse, the reset then only happens while the clock pulse is high (I'm sure my thinking doesn't make any sense here)?

I'm not in school, and have no structured outline to follow, but I'm trying to understand the basic building blocks (including possible shortcomings) before moving on. Otherwise, I'd just go to Wal-Mart and buy myself a clock. That'd be a lot easier (and cheaper), but I wouldn't learn nearly as much.

On using the LS series chips (you can send them to me... I'll buy them ), I don't know enough to choose differently. A few months ago I discovered some very informative and educational videos (Ben Eater's 8-bit breadboard computer). I'm following his lead, while maybe eventually building one for myself (and maybe I can throw in a clock project on the side).

 

So I still don't understand why the tutorial example advertises as a "divide-by-ten" counter, when it only counts from 0-8 (9 complete cycles, not 10). Did they simply make a mistake? Ah, maybe they did..., here's different example, and they used Q3 and Q1: https://www.ee.usyd.edu.au/tutorials/digital_tutorial/part2/counter03.html

ok, consider this topic closed
Thanks guys.

moral of the story: there's a lot of unvetted crap on the internet

 

For now, just a brief intro to the JK flip flop and a little on async and sync circuits.

By using gating to the J and K inputs you can determine what will happen on the next clock, according to the table:
=========================================================
J K state after clock event
0 0 not change from previous state
1 0 Q output goes high, regardless of previous state
0 1 Q output goes low, regardless of previous state
1 1 Q output changes to state opposite that which it was before (toggles)
The not-Q output is always the opposite state of the the Q output, except if the preset and clear inputs are asserted at the same time.

You do the a similar thing with a D-type flip flop where the Q output takes the state of D input at the time of the clock transition. If you simply want to make it toggle, you connect the /Q output to D.
A toggle flip flop changes state with every clock event.

These flip flops, with a few exceptions, are "edge triggered" - it is only the state of the inputs immediately prior to ("set up time") and immediately after ("hold time") the clock edge that matters. Setup time is usually a few nanoseconds for LS. Hold time ranges from zero to a few ns.

Even though the JK flip flop has two inputs requiring gates, it is often the case that fewer gates, overall, are required for a complex circuit.

Systems that change state only on a clock event are referred to as "synchronous" whereas those where state changes occur without need for a clock are called "asynchronous." If you connect a chain for LS90s together to count for several decades, the clock for each decade comes from the output of the previous decade. Each decade is synchronous internally but the overall counter is async from stage to stage and called a "ripple counter" If you have several decades, the increment "ripples" through the chain e.g., in rolling over from 9999 to 0000, the counter actually does this:
9999
9990
9900
9000
0000

The 7490 clocks on the falling edge. The high-order bit of the lowest decade goes high when the count reaches 8, then low at the END of count 9. This roll-over from 9 to 0, then, clocks the next decade.

The in the LS191, each decade has a carry output that is used to enable counting of the subsequent decade. All bits of all decades change state at the same time, but the carry has to ripple through the decades. A fully-sync multi-decade counter takes an awful lot of gates.

(another post just came in; I'm ending this one immediately so as to reduce probable repetition of what others are saying; I'm probably done for today anyway)

 

crap on internet

Years ago, I heard someone on TV say "The good thing about the internet is that anyone can publish anything. The bad thing about the internet is that anyone can publish anything."

 

What do you mean, resets without a clock pulse?
That's not the case here. It resets on the edge of the count of 10 clock pulse which makes it a divide by nine couner.

How can something that goes 0->1->2->3->4->5->6->7->8->9->10..0 be a divide by nine counter. Each -> is a clock pulse. On the clock pulse that takes it from 9->10 the logic requirements are immediately met that issues an asynchronous reset taking the counter back to 0 without the need for another clock pulse. So to go from 0 back to 0 (or any other state back to that same state) takes ten clock pulses. How is that a divide-by-nine counter?

 

ok, consider this topic closed
Thanks guys.

moral of the story: there's a lot of unvetted crap on the internet

There's been a few replies since you posted this. Are you sure you still want to close the thread? If so, I will.

 

There is no contradiction. Here is the difference.

If you want to wire the counters in asynchronous mode and RESET on a given condition, then you want to count to 1010 for 0-9 counter. That will work if all you care about is displaying the numbers on 7-segment displays. For anything else, that design sucks because of everything that others have already stated.

The proper way to design this is to use flip-flops in synchronous mode using finite state machine design techniques.

 

There's been a few replies since you posted this. Are you sure you still want to close the thread? If so, I will.

nah... there's no need to literally close the thread... I'll still read (and learn from) any continued discussion... its just that I'm now satisfied with the answer to my original question. I'm still learning and will come back with more questions, I'm sure.

 

That will work if all you care about is displaying the numbers on 7-segment displays. For anything else, that design sucks because of everything that others have already stated.

And in some ways, that's part of the intent of this design... to teach not only the basics, but also to learn from its shortcomings as well, right?

 

And in some ways, that's part of the intent of this design... to teach not only the basics, but also to learn from its shortcomings as well, right?

Yes... IF the text or tutorial bothers to point out those shortcomings. Sadly, many of them don't. Probably because many (even most) textbook authors have never designed something that had to work reliably in the real world. That's one of the beauties of a forum like this -- you get input from a lot of people that HAVE had to design things in the real world.

 

See