divide by 330 counter

Hi experts,

I am a newbie in electronics, with very little basic knowledge in designing circuits.

I am in need of a circuit for divided by 330 counter. The attached circuit is designed by me. Could you please review the circuit to check whether it will work as a divide by 330 counter?

The main concern is connecting the Q2(output 3) of the third CD4017 to it's ENABLE pin to maintain the high status of Q2 so that when next time the second IC counts 3 , both the inputs of the AND gate will go high which will reset the decade counters.

Actually I have 555 timer, CD4017 and MM74C926N in hand.

your help is highly appreciated so that I will not fry my ICs making wrong connections.

Regards,
AR

 

Pin 13 is the enable (active low) for the 4017. Why are you tying it to Q2 on the 3rd 4017?

Your connections would make it count <200. Did you try setting up one 4017 and step it with a push button to see how many pulses to reach Q9? I think you should use the CO (carry out) at pin 12.

Have you tried the circuit on the breadboard?

Allen

 

I think you have the right idea; detect the "330" count and reset when it is detected, but I haven't worked through your logic for correctness.

My response is to make two points - first, as long as you are careful to not connect two outputs together, you shouldn't damage anything.

Second, and this can get tricky, if a reset signal that is generated by combining the outputs of multiple logic chips is used to reset multiple logic chips, then it can happen that one chip gets reset and cancels the reset signal before all chips get fully reset. That can be very difficult to troubleshoot. One solution to that case would be to extend the reset pulse by using a discrete one-shot pulse generator to produce a fixed-width reset pulse.

 

Wow!!! 74 views and two replies in two hours. I love this forum.

Thanks absf and davebee, for your advises.

@absf: Q2(output 3) is connected to Enable, because when this pin is high, the counter will retain the last output as high until the reset goes low. I need to keep Q2 high until the Q2 of the second IC goes high, which will cause both the inputs of the AND gate goes high, and will make the reset pin of all the counters high, which will restart the process. The count is theoretically correct. Q9 of IC1 will go high at the 10th clock pulse. Q9 of IC2 will go high at 100th CLK pulse and Q2 of IC3 will go high at 300th pulse. Again Q2 of IC2 will go high when the CLK pulse counts 330. I haven't tested this on breadboard bcoz i wanted to confirm the correctness of the connections before switching it ON.
if the enable pin is active low, that means it should be grounded? I referred this link http://www.doctronics.co.uk/4017.htm,it says I can connect any output to ENABLE pin to maintain the highstate of that pin.



@davebee: Thank you for the inputs. As you said I think I will not be frying any IC(it takes three weeks from ebay to deliver an item in my country .

second advice is to be considered, which I haven't thought about. Also the chips should be reset before the 331st CLK goes high, so the reset signal should be short enough as well. do you have any idea to literally "latch" the reset signal?



Regards,
AR

 

a correction
@absf: Q2(output 3) is connected to Enable, because when this pin is high, the counter will retain the last output as high until the ENABLE goes low

 

You could use the 555 timer to give a reset pulse extended, when the 30th and 300th pulses go high (330 pulses) the 4011 chip will go low and trigger the 555 timer to reset the counters, also normally the CE pins will be held low for counting and upon reset will go high to stop further clocking until the reset pulse goes to zero, timed by the 1Meg and 100nF cap on pins 6,7 of the 555.

 

OK, I see your point. But the Enables of 4017 #1 & #2 have to be tied LOW for them to work.

Allen

 

Thank you very much, DodgyDave for the drawing.
I check this on coming days, because O am too busy with my work.

I will get back to all with the results soon.

Regards,
AR