Wikipedia’s definition of DIMM says:

"Most DIMMs are built using "×4" ("by four") or "×8" ("by eight") memory chips with nine chips per side; "×4" and "×8" refer to the data width of the DRAM chips in bits."

So if DRAM chips have 8 bit data width why DIMM has 64 bit data width? I mean doesn’t memory controller issue read or write request to one DRAM chip at a time? If it does what is the purpose of other 56 bits?

 

Computers use buses to connect the various functions and modules. The first microchips used a 4-bit data bus. The DEC PDP-8/S used a 1-bit data path.

An 8-bit data bus is very common because 8-bit data is a convenient size for processing text information.

When working with numbers, 8-bit data is not sufficient and 16, 32 and 64 bits are commonly used. Using an 8-bit data bus to fetch a 64-bit number will require four fetches. A single 64-bit data bus will allow 64-bit access in a single operation, four times faster than an 8-bit bus.

 

Computers use buses to connect the various functions and modules. The first microchips used a 4-bit data bus. The DEC PDP-8/S used a 1-bit data path.

An 8-bit data bus is very common because 8-bit data is a convenient size for processing text information.

When working with numbers, 8-bit data is not sufficient and 16, 32 and 64 bits are commonly used. Using an 8-bit data bus to fetch a 64-bit number will require four fetches. A single 64-bit data bus will allow 64-bit access in a single operation, four times faster than an 8-bit bus.

If u look at the image below all dram chips have seperate data bits,let's suppose that cpu is executing "mov dword ptr [ebp-40h],0Ch" instruction,it will write 32 bit data to specific address,so these 32 bit data will be separated to 4 dram chips in DIMM module or the data will be written to one dram chip by sending 4x8 byte sequentially?

 

The memory chips themselves have 8-bit data paths. Four chips are arranged in parallel to create a single 32-bit data path. Hence a 32-bit access can be performed in a single operation.