Hi everyone,
I’m simulating a bidirectional current limiter using two back-to-back N-channel JFETs. I came across this configuration in an op-amp protection circuit. The circuit seems to work fine—it limits the current regardless of the input voltage (see attached image). However, I noticed that one of the JFETs appears to behave like a diode, and I’m not fully sure why that happens. Could someone explain the reason behind this behavior?
Connetion: Used LT spice for simulation, J113 as njfet. Both sources are connected together and gates are tied together and shorted. (VGS is 0 for both).
Thanks!

 

hi E,
Please post your asc file.
E

 

hi E,
Please post your asc file.
E

Sure, here it is

 

Hi everyone,
I’m simulating a bidirectional current limiter using two back-to-back N-channel JFETs. I came across this configuration in an op-amp protection circuit. The circuit seems to work fine—it limits the current regardless of the input voltage (see attached image). However, I noticed that one of the JFETs appears to behave like a diode, and I’m not fully sure why that happens. Could someone explain the reason behind this behavior?
Connetion: Used LT spice for simulation, J113 as njfet. Both sources are connected together and gates are tied together and shorted. (VGS is 0 for both).
Thanks!
View attachment 354608

Start with the constitutive equation for the JFET and then apply the constraint imposed by shorting the gate to the source.

 

Start with the constitutive equation for the JFET and then apply the constraint imposed by shorting the gate to the source.

Can you brief little more? what I believe the N channel is pinching off and Drain to Gate acts like a PN diode. If so how the pinching is happening when VGS is zero? or if I am wrong can you explain me about this little more? thanks

 

hi E,
Look over the device description notes on the datasheet for the J113 device.
Especially figs #3 and #4.

E

 

A JFET will pass a current Idss when the gate to source voltage, Vgs is equal to 0. Reducing the gate to source voltage to a negative value will pinch off the channel. An increasingly positive Vgs will cause the drain current to rise until the device is destroyed.

 

A JFET will pass a current Idss when the gate to source voltage, Vgs is equal to 0. Reducing the gate to source voltage to a negative value will pinch off the channel. An increasingly positive Vgs will cause the drain current to rise until the device is destroyed.

Yeah I get it, but here in this circuit the VGS will be always zero right? so it should act like a resistor limiting the current to IDSS as you said. But here one of the JFET is acting as diode and droping 0.6 to 0.7v. Which is what I am confused of. I believe VDS is controlling the channel width based on the polarity of the voltage and at some point the channel pinches off and Drain-Gate acts as diode. If I am correct here, how channel width is controlled? if I am wrong what makes the JFET to drop voltage exactly as a diode? Thanks

 

I think, I was missing a simple concept of diode resistance when it is biased. Since Drain to Gate is forward biased it offeres less resistace than the Drain to Source channel resistance. That is why the voltage drop is similar to that of diode and almost no current is limited. I believe I missed a simple and basic concept. Thank you for the guidence provided.

 

JFETs can be used as low-leakage diodes, but it is usually done by joining source and drain together, not source and gate.

 

Hi Ear.
Did you read this section of the d/s?
E

 

Hi Ear.
Did you read this section of the d/s?
E
View attachment 354647

Hi Eric,

Yeah I read datasheet, Indeed it is intereseting to know that Drain and source are interchangable. I even tried that in LT spice and results are same. So for this JFETthe Vgs and Vgd are same.

 

Depending on which of the two regions of operation, Saturation or Triode region.
A (VCR) voltage controlled resistor in one region or in the triode region an N-Channel Jfet can exhibit positive gain.
it is applying a meaningful voltage correctly to the circuit that the substrate can exibit current direction or diode.

 

Depending on which of the two regions of operation, Saturation or Triode region.
A (VCR) voltage controlled resistor in one region or in the triode region an N-Channel Jfet can exhibit positive gain.
it is applying a meaningful voltage correctly to the circuit that the substrate can exibit current direction or diode.

Hi Sparky,

Thanks for replying, that's a straightforward and perfect answer. Thanks!