When I need to use a bypass capacitor ?

Thread Starter

Oussama Zaidi

Joined Mar 1, 2016
53
Hi
Can you tell me in which cases, in general, I need to use a bypass or decoupling capacitors and how to calculate their values in the case of a DC signal.
 

shteii01

Joined Feb 19, 2010
4,644
You use them on power supply lines. They are there to supply power to your IC for a few milliseconds in case the power supply suddenly can not supply it. Since you are dealing with power supply lines, there are no DC signals.

The values don't really matter because, again, the job of the capacitor is to supply power for a few milliseconds. The important IC like microcontrollers list the capacitor values in their datasheet, you can use the same capacitors on all your IC.
 

MrChips

Joined Oct 2, 2009
21,278
Since one is expected to put decoupling capacitors on the board, one does not always show it in the circuit diagram.
Electronic design and board layout programs now expect all components to be entered and thus expect you to insert and place all components.

Similarly, digital circuit schematics will sometimes not show Vcc and GND pins, or Vdd and Vss pins.

Where do decoupling capacitors go on the board?

You would put 100nF ceramic caps between Vsupply and GND pins as close as possible at the IC pins, keeping all leads and physical traces as short as possible. For this reason, SMD components have better performance than thru-hole components. It is recommended that a 100nF capacitor be placed at every IC.

In sensitive analog circuits, it is recommended practice to put a 10μF electrolytic in parallel with the 100nF ceramic.

The reasons for this are explained in this application note:

http://www.intersil.com/content/dam/Intersil/documents/an13/an1325.pdf
 

andrewmm

Joined Feb 25, 2011
369
You can not put to much decoupling on a circuit, but you can put to little.

If you put to little, the faults can be very hard to find.
 

shteii01

Joined Feb 19, 2010
4,644
I mean where I need to put them exactly I don't see capacitors everywhere in the circuits, did I need them just in the supplies of the ICs or in other places too...something like that.
When I first replied to your thread here, I pulled uc ic datasheet and I pulled NOT gate ic datasheet. I looked at their recommended circuits, guess what I found? uC ic datasheet showed decoupling capacitors. The simple NOT gate ic DID NOT show decoupling capacitors. So. The uC ic manufacturer clearly telling you that you REALLY want those decoupling capacitors to be there. The NOT gate ic, well, it is up to you.
 

WBahn

Joined Mar 31, 2012
25,899
You can not put to much decoupling on a circuit, but you can put to little.

If you put to little, the faults can be very hard to find.
Actually, you CAN put too much and hurt circuit performance, particularly from the standpoint of noise, by doing so.

The problem is that there is no such thing as a pure capacitor, so any real capacitor comes with parasitic resistance and inductance and those parasitic values tend to be a function of capacitance (due to the nature of how capacitors are physically constructed). So if you use too large of a capacitor, you can easily end up with a device that looks more like an inductor at the very frequencies where need it to be capacitive.

The best solution is to consider each circuit case-by-case. But for most circuits (beyond the low-speed circuits where even brutish rules-of-thumb are often adequate) a reasonable cookie-cutter approach is to use decade-tiering where you put several capacitors in parallel that step down in value by either 10x or 100x and by minimizing the lead distance of the smallest valued capacitors as much as possible (i.e., putting more emphasis on doing it for the smaller values relative to the large values).
 

jpanhalt

Joined Jan 18, 2008
9,663
Actually, you CAN put too much and hurt circuit performance, particularly from the standpoint of noise, by doing so.

The problem is that there is no such thing as a pure capacitor, so any real capacitor comes with parasitic resistance and inductance and those parasitic values tend to be a function of capacitance (due to the nature of how capacitors are physically constructed). So if you use too large of a capacitor, you can easily end up with a device that looks more like an inductor at the very frequencies where need it to be capacitive.

The best solution is to consider each circuit case-by-case. But for most circuits (beyond the low-speed circuits where even brutish rules-of-thumb are often adequate) a reasonable cookie-cutter approach is to use decade-tiering where you put several capacitors in parallel that step down in value by either 10x or 100x and by minimizing the lead distance of the smallest valued capacitors as much as possible (i.e., putting more emphasis on doing it for the smaller values relative to the large values).
So, what process do you use to decide NOT to use a decoupling capacitor? That is, your next sentence seems to contradict your first sentence, and I was wondering how you distinguish between the two and determine when one should not add decoupling.

John
 

WBahn

Joined Mar 31, 2012
25,899
So, what process do you use to decide NOT to use a decoupling capacitor? That is, your next sentence seems to contradict your first sentence, and I was wondering how you distinguish between the two and determine when one should not add decoupling.

John
Huh?

Where did I say or imply that the only alternative to using too much decoupling capacitance is to use none at all? I was very explicitly responding to the claim that, "You can not put to much decoupling on a circuit, but you can put to little." and pointing out that, in fact, you CAN put too much decoupling in a circuit. I further pointed out the issues that can result in this happening and a common way that often deals with the problem -- and note that that approach most definitely DOES use decoupling capacitors.

Where is this contradiction of which you speak. You underlined the statement that the best solution is to consider each circuit case-by-case. The next sentence then offers an approach that, for most circuits, is good enough. It isn't as good as the best approach, it is merely good enough. There are also many circuits for which it is NOT good enough (hence the phrase "But for most circuits" as opposed to "for all circuits".

The issue isn't deciding between using decoupling or not using decoupling, it is between using sufficient decoupling capacitance and using too much. If you use such a large capacitor that the self-resonance frequency is lower than the frequency of the noise you are trying to bypass, then you have a problem.
 

ronv

Joined Nov 12, 2008
3,770
Once upon a time...... I worked on a solid state disk for mainframes. It had about 100 big boards with about 100 memory chips and drivers per board. Every chip had 100 nf cap, but they weren't super reliable. Long story short one would pop about every 2 months. This might not have been to bad as of course that little cap couldn't blow the huge breaker, but it splattered conductive stuff all over the board next to it. The "fix" was to have the field engineers clip all but 1 a row off the boards.
Moral of the story. Every part has a failure rate.
 

jpanhalt

Joined Jan 18, 2008
9,663
This note from TI presents a practical and non-defensive discussion of what to avoid doing in decoupling: http://www.ti.com/lit/an/sloa069/sloa069.pdf

I found the discussion on pages 7 and 8 particularly interesting with respect the popular approach of using decade-tiered capacitors.

John

Edit: Corrected link. Thank you @WBahn for mentioning. I had been updating my folder on decoupling and simply didn't notice the wrong link.
 
Last edited:

hp1729

Joined Nov 23, 2015
2,304
Hi
Can you tell me in which cases, in general, I need to use a bypass or decoupling capacitors and how to calculate their values in the case of a DC signal.
All the advice given so far is good. Now, for the real world, for small circuits with only a few ICs I often omit them completely. But there is no wisdom in taking bad advice. :)
Build your circuit without them and see if you have a problem. No problem, then no need for a solution.
Calculation? It might depend on the current drawn by the I you are connecting it to, but usually 100 nF is fine. Large scale TTL chips, maybe more, but nobody uses such chips as the DC310 any more.
 

MrChips

Joined Oct 2, 2009
21,278
Build your circuit without them and see if you have a problem. No problem, then no need for a solution.
Bad advice.

Same as someone who says,

"I never use ESD protection and I've never experienced a problem".

"I never wear a bike helmet and I'm still alive".

"I never wear a seat belt, why worry now".
 

WBahn

Joined Mar 31, 2012
25,899
I fixed the link. The Murata excerpt is nice, but I could not trace the title to its complete document. However, here is a link to a more complete piece from Murata: http://www.murata.com/~/media/webrenewal/support/library/catalog/products/emc/emifil/c39e.ashx?la=en-us

John
Thanks.

Murata has some pretty nice tech materials. But this is generally true of many major device manufacturers -- and it makes sense. They are in the business of selling components that are used to solve problems and if they do a good job of providing the information needed to get good solutions to those problems, people will tend to buy their components over their competitors. Certainly it doesn't always work out that way, but it does often enough to make the effort worth it.
 
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