Do you still need a bypass cap for every ic if..
- Thread starter tpny
- Start date
0.1μF is a bit large to build into the IC.
You can buy IC sockets that come with bypass caps between certain pins.
http://www.digikey.com/product-detail/en/110-93-314-41-801000/ED2101-ND/33731
http://www.digikey.com/scripts/dksearch/dksus.dll
You can buy IC sockets that come with bypass caps between certain pins.
http://www.digikey.com/product-detail/en/110-93-314-41-801000/ED2101-ND/33731
http://www.digikey.com/scripts/dksearch/dksus.dll
Perhaps, it takes up too much real-estate and/or costs too much at the silicon level? However, I do remember when some of the socket manufacturers had sockets with built-in bypass caps...
Yes. I remember looking at a picture of the old 741 chip, which has a 30pF capacitor on-chip, and the capacitor took up a significant amount of the total chip area.
The rule-of-thumb that I always saw was to use a 0.1 uF X7R ceramic in parallel with a plain 10 uF electrolytic, right at every power pin.
A lot depends on what the chips are doing, i.e. what kinds of transient current demands their power pins will be presenting. High-frequency-"bypassing" capacitors are good for amplifiers (discrete BJT ones too), since there is a sneak HF positive feedback path that needs to be shorted for HF.
The other main thing that we need the local caps for is "decoupling" of the supplies. Think of the caps as small point-of-load power supplies. And remember that any length of power supply or ground rail has self-inductance, and V = L x di/dt. When a change in current is demanded through a power pin, the local decoupling caps need to be able to supply its leading edge. Otherwise, without decoupling caps, besides the possibility that the current might not be able to rise fast-enough because of the rails' inductances, it WOULD cause a rail voltage disturbance, due to V = L di/dt, when trying to pull a fast-rising (or falling) current through the rail inductance.
We can easily get a rough estimate of the needed decoupling capacitance by looking at a "delta-ized" version of the capacitor equation, I = C dv/dt, solving for C and changing to a "small delta-time" version: C = delta I x delta t / delta v. Then take the worst-case (largest) current change and the shortest time in which it might need to occur (both probably from the chip's specs), and also pick the worst-case voltage disturbance that we would want to allow it to cause on the power rail, delta v.
So, for example, for an LM3886 audio amplifier chip, we might see the maximum slew-rate of 19 V/μs for 1.5 microseconds with a 4 Ohm load, implying a delta I of 7.125 Amps. So we'd get C = 7.125 x 1.5 / delta v, or about 10.7 / delta v. If we were willing to see a rail disturbance of up to delta v = 0.1 volt (with a 28.5-volt rail), we would want at least 107 μF just for decoupling purposes.
We can also think of it as coming up with a "target impedance", as seen by the power/gnd pins, by using the worst-case maximum delta I and the desired maximum delta V, so that delta V max / delta I max = target impedance max, e.g. 0.1 Volts / 7.125 Amps = 14 milliOhms max impedance (as seen by the chip's power/gnd pins). Then we'd need to maintain that impedance (or less), up through the frequencies of interest. For edges, the equivalent frequency can be calculated as f = 1 / (π x trise).
We might also want to make sure that the decoupling caps' total lead length plus PCB trace length plus any decoupling cap intrinsic inductance is small-enough. Maybe we could use the inductance equation, V = L di/dt and do something similar, as in L = delta V x delta t / delta I = 0.1 x 1.5μs / 7.125 = 21 nH. Wow, that's probably equivalent to only about one inch total round trip of pcb trace or wire plus the lead-spacing of the cap! That's getting tight even for only a 100 uF electrolytic. Multiple parallel caps might need to be used, but note that for the total resulting inductance to be fully reduced by paralleling, the way total resistance reduces when paralleling resistors, there can be no mutual inductance, which means that the conductors from the caps to the point of decoupling can't be shared, i.e. use parallel caps but also with parallel conductors for each cap, that stay separate all the way to the chip's power and ground pins.
For digital chips, the inductance needs to be kept really low. And the inductance of most caps is mainly a function of the physical size or lead-spacing. So, if possible, use surface-mount caps, right across the pins. And even better, use the ones that have the connections along the longer edges, to minimize the distance across the caps. Using true power and ground planes can help immensely. Then you can even spread the decoupling caps around. but try to position them so that they all use different paths, for their currents, to get the maximum inductance-reducing effect from paralleling them. I would also think that the power and ground connections to the planes would need to be paralleled, and distributed, physically, in order to make the currents take as many separate paths as possible, if the lowest inductance is needed.
A lot depends on what the chips are doing, i.e. what kinds of transient current demands their power pins will be presenting. High-frequency-"bypassing" capacitors are good for amplifiers (discrete BJT ones too), since there is a sneak HF positive feedback path that needs to be shorted for HF.
The other main thing that we need the local caps for is "decoupling" of the supplies. Think of the caps as small point-of-load power supplies. And remember that any length of power supply or ground rail has self-inductance, and V = L x di/dt. When a change in current is demanded through a power pin, the local decoupling caps need to be able to supply its leading edge. Otherwise, without decoupling caps, besides the possibility that the current might not be able to rise fast-enough because of the rails' inductances, it WOULD cause a rail voltage disturbance, due to V = L di/dt, when trying to pull a fast-rising (or falling) current through the rail inductance.
We can easily get a rough estimate of the needed decoupling capacitance by looking at a "delta-ized" version of the capacitor equation, I = C dv/dt, solving for C and changing to a "small delta-time" version: C = delta I x delta t / delta v. Then take the worst-case (largest) current change and the shortest time in which it might need to occur (both probably from the chip's specs), and also pick the worst-case voltage disturbance that we would want to allow it to cause on the power rail, delta v.
So, for example, for an LM3886 audio amplifier chip, we might see the maximum slew-rate of 19 V/μs for 1.5 microseconds with a 4 Ohm load, implying a delta I of 7.125 Amps. So we'd get C = 7.125 x 1.5 / delta v, or about 10.7 / delta v. If we were willing to see a rail disturbance of up to delta v = 0.1 volt (with a 28.5-volt rail), we would want at least 107 μF just for decoupling purposes.
We can also think of it as coming up with a "target impedance", as seen by the power/gnd pins, by using the worst-case maximum delta I and the desired maximum delta V, so that delta V max / delta I max = target impedance max, e.g. 0.1 Volts / 7.125 Amps = 14 milliOhms max impedance (as seen by the chip's power/gnd pins). Then we'd need to maintain that impedance (or less), up through the frequencies of interest. For edges, the equivalent frequency can be calculated as f = 1 / (π x trise).
We might also want to make sure that the decoupling caps' total lead length plus PCB trace length plus any decoupling cap intrinsic inductance is small-enough. Maybe we could use the inductance equation, V = L di/dt and do something similar, as in L = delta V x delta t / delta I = 0.1 x 1.5μs / 7.125 = 21 nH. Wow, that's probably equivalent to only about one inch total round trip of pcb trace or wire plus the lead-spacing of the cap! That's getting tight even for only a 100 uF electrolytic. Multiple parallel caps might need to be used, but note that for the total resulting inductance to be fully reduced by paralleling, the way total resistance reduces when paralleling resistors, there can be no mutual inductance, which means that the conductors from the caps to the point of decoupling can't be shared, i.e. use parallel caps but also with parallel conductors for each cap, that stay separate all the way to the chip's power and ground pins.
For digital chips, the inductance needs to be kept really low. And the inductance of most caps is mainly a function of the physical size or lead-spacing. So, if possible, use surface-mount caps, right across the pins. And even better, use the ones that have the connections along the longer edges, to minimize the distance across the caps. Using true power and ground planes can help immensely. Then you can even spread the decoupling caps around. but try to position them so that they all use different paths, for their currents, to get the maximum inductance-reducing effect from paralleling them. I would also think that the power and ground connections to the planes would need to be paralleled, and distributed, physically, in order to make the currents take as many separate paths as possible, if the lowest inductance is needed.
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