could you explain why you are stating an ideal square wave at the output? What would make you want to assume that?

This assumption together with Vth = 1/2Vcc should simplify the calculation a lot ( the average voltage across the capacitor must be equal to 1/2Vcc ).

 

The noise coupled with the gain of each inverter should, under "normal"
designs with "normal" scaled Z's, C and R, start the osc.

I have seen a paper where G of gate was calculated to be ~ -27.

Of course G is impacted by supply, T, process......

Regards, Dana.

 

This is one of those circuits where it is much faster to make a good guess, and then adjust values until you get the desired results. Much faster as well.

 

This assumption together with Vth = 1/2Vcc should simplify the calculation a lot ( the average voltage across the capacitor must be equal to 1/2Vcc ).

Hello again,

I am asking how you would enforce this condition on the circuit for the purpose of analysis. The condition where the output is a square wave.

Also, what else is interesting is that if we trace the signal around the loop we find that it has negative feedback, which might imply that the output would be 1/2 Vcc (or 1/2 Vdd), a constant DC voltage regulated at 1/2 the supply voltage.

 

The noise coupled with the gain of each inverter should, under "normal"
designs with "normal" scaled Z's, C and R, start the osc.

I have seen a paper where G of gate was calculated to be ~ -27.

Of course G is impacted by supply, T, process......

Regards, Dana.

Hi,

Notice the feedback path shows a negative feedback system.

 

This is one of those circuits where it is much faster to make a good guess, and then adjust values until you get the desired results. Much faster as well.

Hello there,

I am starting to question if the circuit works at all, reliably, due to the negative rather than positive feedback.

 

If this were a linear circuit it would indeed not oscillate. But it is not linear, instead, two logic states are chasing each other around the loop. The RC time constants slow it down to some potentially useful frequency. AND, the average value of the output of the perfect version does average to half the supply voltage. But the average is never the same as the instant value of the output.
Next, if you follow the logic values around the loop it becomes clear that it will never be stable, because there are an odd number of inversions. What is important here is that logic inverters are not linear devices, and so linear analysis may only hold during the state change, if at all.

 

If you look at the loop the gate(s) provide 3 x 180 degrees phase shift.

The RC would need to provide the other 180 to get positive feedback. But
RC only in the limit generate 180, and at the limit their output amplitude is
close to zero. Read need even more G thru the gates.

So to your point its definitely a marginal design.

Why does it work, my guess is the little additional Tpd thru gates adds to
the phase shift from RC to get the 180 and still have enough signal left
to gain up into oscillation ?

Regards, Dana.

 

If you look at the loop the gate(s) provide 3 x 180 degrees phase shift.

The RC would need to provide the other 180 to get positive feedback. But
RC only in the limit generate 180, and at the limit their output amplitude is
close to zero. Read need even more G thru the gates.

So to your point its definitely a marginal design.

Why does it work, my guess is the little additional Tpd thru gates adds to
the phase shift from RC to get the 180 and still have enough signal left
to gain up into oscillation ?

Regards, Dana.

My point is that it is a NON-linear circuit, and certainly the RC time constants do provide the rest of the phase shift at the actual operating frequency. And, of course, a loop of three gates directly connected is indeed a very marginal design, at best. I mentioned that to point out that the circuit must oscillate because it has no static stable state

 

My point is that it is a NON-linear circuit, and certainly the RC time constants do provide the rest of the phase shift at the actual operating frequency. And, of course, a loop of three gates directly connected is indeed a very marginal design, at best. I mentioned that to point out that the circuit must oscillate because it has no static stable state

Hi,

Yes, but just saying it is non linear does not mean that it oscillates, and saying that it has no stable state does not mean that it oscillates in any meaningful way. That is what i am pointing out, and so 'marginal' design does apply here, but it may not even be that good
What we need to know in order to verity that it is workable is we need to know the exact mechanism that determines oscillation, and that mechanism is repeatable.

Consider that the RC does NOT slow it down much, What then? It remains mostly linear, which ends up being a negative feedback amp or an oscillator that oscillates between 2.49v and 2.51v, meaning a very unstable oscillation even though the output of one of the gates could still be rectangular.
I agree that the time delays in the gate will play a big part of it, and that can vary.

My conclusion is that i would not use this design but change the gates to all Schmitt Trigger gates and suddenly we have a workable design. Either that or that plus use a buffer Schmitt Trigger for the last stage. We might try that also.

I did a linear analysis and found that two inverters plus one buffer produces sinusoidal components, while three linear inverters produce only a single exponential with offset. Neither are worth using though.

 

If you look at the loop the gate(s) provide 3 x 180 degrees phase shift.

The RC would need to provide the other 180 to get positive feedback. But
RC only in the limit generate 180, and at the limit their output amplitude is
close to zero. Read need even more G thru the gates.

So to your point its definitely a marginal design.

Why does it work, my guess is the little additional Tpd thru gates adds to
the phase shift from RC to get the 180 and still have enough signal left
to gain up into oscillation ?

Regards, Dana.

Hi,

Yes, very strange design. Change all the gates to Schmitt Trigger gates and then we have something much more predictable.

 

OK, when I said "non-linear" I should have said "binary digital", that is, having only two states, 0 and 1. Clearly an error on my part. And then my point about not having a stable state makes more sense, because there is always a 1 chasing the zero around the loop. At that point the RC delay is what keeps the frequency down to a usable value, since otherwise the oscillation period is only the sum of response delays and transition times as the zero and one race around the loop.
Fortunately, real digital devices mostly have a bit of hysteresis in their response to input levels. That is provided to allow operation with less than perfect square waveforms, frequently found in the real world. But different brands have different amounts of hysteresis, which can lead to a design that worked well with one brand of IC not working correctly with a different brand. I offer my thanks to DigiKey for being able to provide the same part from different brands, they saved a whole production run for me a few years back. Sometimes a little thing like an unspecified IC parameter can make a huge world of difference! Not all schmidt trigger inputs are the same, even though the part numbers are identical.

 

OK, when I said "non-linear" I should have said "binary digital", that is, having only two states, 0 and 1. Clearly an error on my part. And then my point about not having a stable state makes more sense, because there is always a 1 chasing the zero around the loop. At that point the RC delay is what keeps the frequency down to a usable value, since otherwise the oscillation period is only the sum of response delays and transition times as the zero and one race around the loop.
Fortunately, real digital devices mostly have a bit of hysteresis in their response to input levels. That is provided to allow operation with less than perfect square waveforms, frequently found in the real world. But different brands have different amounts of hysteresis, which can lead to a design that worked well with one brand of IC not working correctly with a different brand. I offer my thanks to DigiKey for being able to provide the same part from different brands, they saved a whole production run for me a few years back. Sometimes a little thing like an unspecified IC parameter can make a huge world of difference! Not all schmidt trigger inputs are the same, even though the part numbers are identical.

Hi again,

Oh ok so you are just commenting on the general operation of the circuit, that's cool too

What do you think about the tiny voltage change issue? That's where the output of a gate is still digital (non linear, binary) but the voltage across the cap only changes by a very small amount per cycle, like as little as 10mv. That looks bad to me because even noise will change the duty cycle of the binary output so each cycle will have a different pulse width. I think that is very bad. That means some cap and resistor values are better than others, which is strange for an oscillator that we think at first should be able to have any cap and resistor value (other than loading too much of course).
If you get a chance to try different R and C values you'll see this right away. The simulations starts out as a ramp that goes up toward 2.5v, then starts to jump up and down by a very tiny amount. Each tiny jump up then down constitutes one cycle of the digital output (either 5v or 0v roughly).
Schmitt Trigger oscillators dont do that because they require at least some much change at the input, at least a volt or so.

 

This oscillator circuit is subject to phase noise, like a lot of oscillator circuits. There is no question about that. BUT most real world CMOS IC devices have a bit of differential between the voltage that initiates a change in one direction and the voltage that initiates a change in the opposite direction. That difference is intentional and very important to the functioning of most digital logic. So while the noise effect that you described would be a serious problem in a theoretical inverter, in a typical inverter there is enough differential to avoid any objectional behavior. On many devices there is published a minimum input signal slew rate to avoid the problem. That is why the actual circuit in most IC devices is a lot more complicated than the published functional circuit.
That is also why some types of inverters are a poor choice for this type of oscillator. "All inverters are NOT created equal".

 

This oscillator circuit is subject to phase noise, like a lot of oscillator circuits. There is no question about that. BUT most real world CMOS IC devices have a bit of differential between the voltage that initiates a change in one direction and the voltage that initiates a change in the opposite direction. That difference is intentional and very important to the functioning of most digital logic. So while the noise effect that you described would be a serious problem in a theoretical inverter, in a typical inverter there is enough differential to avoid any objectional behavior. On many devices there is published a minimum input signal slew rate to avoid the problem. That is why the actual circuit in most IC devices is a lot more complicated than the published functional circuit.
That is also why some types of inverters are a poor choice for this type of oscillator. "All inverters are NOT created equal".

Hi again,

If that were true then it would be very small, and i dont think it works that way.
You can notice that if you use a large value resistor you can bias the inverter into the linear mode. If there were upper and lower thresholds, that would not be possible. It does not bang from one state to the other either, it stays perfectly linear.
The internal high gain is what develops the logic-like behavior. If the gate was biased into linear operation and then the input was raised very very slightly, the output would fall (or rise in the case of a buffer) very slighty, and so with some input change the output would eventually reach saturation either high or low.

But the problem i am talking about is not just a minor drawback, it's a total wipeout. What it would cause in the real world is not an oscillator that we can adjust, but an oscillator that ends up being frequency modulated as much as 200 percent or more, which means the frequency would be changing all the time in very gross ways. That pushes it into a category that is outside of just a not-so-good oscillator but makes it unusable in any but the most arcane, esoteric applications like a random number generator.

Maybe i should show a few waveforms to illustrate this problem. Most oscillators have a very wide range of voltage changes at every point in the circuit that is capable of controlling anything. This circuit could have a plus and minus 10mv peak to peak amplitude triangle that determines the frequency of the output digital wave. The propensity for very severe noise interference with the frequency of the digital wave is just too great to be reliable. This means that some values of R and C wont work.
I suppose we could investigate that further.