You aren't going to learn about what you're asking in a CS program.
You need to clearer about what technology you're referring to. Resistors implies RTL because most technologies avoid them as much as possible because they take a lot of real estate. When you say transistors, do you mean BJTs or MOSFETs? It makes a difference.

In an IC, there aren't separate pieces of doped silicon next to each other. A process starts with an N or P type silicon wafer and regions of the opposite polarity are implanted or deposited. Many die are fabricated on the same silicon wafer and separated after test for packaging.
A cross section of more than an inverter is pretty much impossible. The way these devices are drawn, the N devices are grouped together and the P devices are grouped together (for CMOS). It's done that way to minimize the number of P regions that need to be separated from N regions.

Now you've really gone and thrown the poor CS into the deep end.

 

I'm looking for a graphic

Layout for an inverter using an N-well process:

Node A is the input, node Y is the output. Forgot to draw the line to metal, it's blue.

The NOR gate example I mentioned earlier would draw the two P devices in the same nwell to avoid a well to well space penalty.

 

Thank you for your reply, however what i'm looking for is what is actually happening in the chip, not necessarily the graphic
representation. What I mean is, in an NP transistor we have a two pieces of dopped silicon next to each other and taking
advantage of their electron properties we can get voltage to move across them. I'm very new to all this so I don't understand
why transistors and resistors are so vital or really what the words mean, but I know they are and somehow they work like switches.
What I'm looking for a graphic (less the schematic and more of a literal) or a very "for dummies" explanation of what's going on in the chip?
Is it a combination of NPs that
are next to each other and when the current is applied to both ends or one end that it behaves as an OR or AND or NOT?
Please excuse my use of the word "current" and "voltage" I know they have technical meanings so if i used it wrong please correct me,
but this is what im trying to figure out.

Let's consider CMOS circuits, as these are arguably the easiest to understand at the level I think you are looking for.

Do you have a basic idea of how a PN junction diode works? For our purposes here we can gloss over the nitty-gritty details and say that we have two basic types of doped silicon -- N-type, which has excess electrons and P-type which has excess holes (a hole being a place where an electron would like to be but for which there aren't enough electrons to fill). Both types conduct current fairly easily. However, when you have N-type material adjacent to P-type material the excess electrons from one diffuse into the excess holes in the other and the result is a region at the junction that has neither excess electrons nor excess holes and now you have an insulator that doesn't conduct current well at all. But as you apply a voltage across the junction, the electrical field will try to pull the electrons in the opposite direction of the field. Applied one way, this will actually cause this barrier region to grow and make it even harder for current to flow. But applied the other way it will cause the barrier region to narrow and make it possible for current to flow across it. This is, very crudely, how a PN junction diode works.

Now imagine three regions of doped semiconductor -- we have two N-type regions separated by a P-type region (this is the basic structure of an N-type Field Effect Transistor, or NFET). Now if we apply a voltage across the two N-type regions it doesn't matter what the polarity is, we will widen the barrier region at one of the two PN junction regions. But what if we could apply an external field sideways across the middle P-type region so that we pull enough electrons to one edge that we end up with an excess of electrons along this strip? Now we have, effectively, an N-type channel between the two N-type ends and current can flow. This sideways field is due to the voltage applied to the gate terminal and the higher the voltage, the wider the channel. In digital circuits we either apply no gate voltage or we apply a strong gate voltage; this makes the transistor act like a switch where a LO voltage to the gate opens it and a HI voltage at the gate closes it. We can build another type of transistor that behaves similarly but uses two P-type regions separate by an N-type region; in this case, a LO voltage on the gate closes the switch while a HI voltage opens it. With these two types of voltage-controlled switches we can construct any type of binary logic gate we want.

EDIT: Correct a couple minor typos.

 

Let's consider CMOS circuits, as these are arguable the easiest to understand at the level I think you are looking for.

Do you have a basic idea of how a PN junction diode works? For our purposes here we can gloss over the nitty-gritty details and say that we have to basic types of doped silicon -- N-type, which has excess electrons and P-type which has excess holes (a hole being a place where an electron would like to be but for which there aren't enough electrons to fill). Both types conduct current fairly easily. However, when you have N-type material adjacent to P-type material the excess electrons from one diffuse into the excess holes in the other and the result is a region at the junction that has neither excess electrons nor excess holes and now you have an insulator that doesn't conduct current well at all. But as you apply a voltage across the junction, the electrical field will try to pull the electrons in the opposite direction of the field. Applied one way, this will actually cause this barrier region to grow and make it even harder for current to flow. But applied the other way it will cause the barrier region to narrow and make it possible for current to flow across it. This is, very crudely, how a PN junction diode works.

Now imagine three regions of doped semiconductor -- we have two N-type regions separated by a P-type region (this is the basic structure of an N-type Field Effect Transistor, or NFET). Now if we apply a voltage across the two N-type regions it doesn't matter what the polarity is, we will widen the barrier region at one of the two PN junction regions. But what if we could apply an external field sideways across the middle P-type region so that we pull enough electrons to one edge that we end up with an excess of electrons along this strip? Now we have, effectively, an N-type channel between the two N-type ends and current can flow. This sideways field is due to the voltage applied to the gate terminal and the higher the voltage, the wider the channel. In digital circuits we either apply no gate voltage or we apply a strong gate voltage; this makes the transistor act like a switch where a LO voltage to the gate opens it and a HI voltage at the gate closes it. We can build another type of transistor that behaves similarly but uses two P-type regions separate by an N-type region; in this case, a LO voltage on the gate closes the switch while a HI voltage opens it. With these two types of voltage-controlled switches we can construct any type of binary logic gate we want.

Wow things are getting so much clearer, okay I need to do some digging to better visualize what you're saying but it makes a lot of sense.
My idea of what was going on in the IC was really off. We have been learning about clock cycles is this what is creating the HIGH and LO voltage?

 

We have been learning about clock cycles is this what is creating the HIGH and LO voltage?

Clocks can generate the signal to control the timing of the logic signal changes, but many logic signals are just the output from other logic gates.

 

Thank you this, is starting to clear things up, what is buffering?

Buffering can do one (or a combination) of things, depending on the situation. In digital circuits a buffer is commonly used to increase the drive strength of a circuit since most basic digital circuits can't supply much current if we want them to be fast. But this is usually fine as usually they are only driving a small number of other logic gates which don't require much current at the input to operate. But if we are driving a lot of gates (what is called "high fanout") or if we are driving heavier loads then we insert a buffer.

The other very common use for a buffer is to prevent the load from affecting the logic operation of the gate itself. This is particularly important for "latch" circuits that remember what state they are in. If the outputs are not buffered, then a heavy load can prevent them from storing the state they are supposed to or even change the state that is stored in them. This is generally considered "a bad thing" -- but not always; there are latch circuits in which the only way to change the state is to deliberately overdrive the output in order to affect the logic operation. In general, tricks like this are only done within circuits completely contained within the same IC, so most people don't have to worry about it -- the interface between the IC and the rest of the world is almost always buffered.

Another use of buffering, but usually not that important in digital circuits that have adequate drive strength, is to restore a digital voltage to its proper levels. In some logic families (or ad-hoc logic circuits) the output voltage from a gate may be a function of the voltage at the input (for voltages that are the same logic level) and thus for weak input signals might be closer to the edge of the defined logic levels and if we send it through another gate that has the same effect, we might end up with an output signal that is not clearly either a HI or a LO. So a buffer can restore the degraded signal to its proper level before sending it on. Most modern digital logic families are inherently restorative -- as long as the input signal is within tolerances the output will be at the proper level regardless of how close the input signal is to the margin. So you usually only see these kinds of buffers when something is in between the output of one gate and the input of another gate that can cause the signal to degrade too far -- such as a long transmission link or something that is injecting a lot of noise into the signal.

 

Wow things are getting so much clearer, okay I need to do some digging to better visualize what you're saying but it makes a lot of sense.
My idea of what was going on in the IC was really off. We have been learning about clock cycles is this what is creating the HIGH and LO voltage?

No. The clock signal is used to control when things happen in the circuit. The signal voltages themselves are produced by the gates themselves (with the clock signal just being one particular logic signal).

 

Wow things are getting so much clearer, okay I need to do some digging to better visualize what you're saying but it makes a lot of sense.
My idea of what was going on in the IC was really off. We have been learning about clock cycles is this what is creating the HIGH and LO voltage?

Wow! You got lots of good answers there on so many levels. These guys are great, aren't they?

 

Wow! You got lots of good answers there on so many levels. These guys are great, aren't they?

Absolutely, these are some of the best answers I've seen on any forum, just a little painful that I am such a novice.

 

Wow! You got lots of good answers there on so many levels. These guys are great, aren't they?

Yep. This Thread is pretty much the whole chapter on AND gates from 3 or 4 different books and 5 or 6 different points of view.

just a little painful that I am such a novice.

Take the posts that address your level of competence and ignore the posts you can't understand...or work on them later.
That's why we have half a dozen ways to approach this. Somebody on this site almost always manages to make the right connection for the Thread Starter. Often enough, it's not me. But put them all in a pile and you almost always get a few that communicate.

 

That's a buffered OR gate.

I questioned it because RCA's stated method for creating buffered logic from unbuffered was to De Morganize. The schematic I posted doesn't conform to their stated methodology.

This brings up another issue - compatibility. According to RCA, some manufacturers were marketing buffered devices in a way that confused them with unbuffered. Unbuffered gates are faster, but have about twice as much input capacitance and lower noise immunity.

The buffered gate I posted only has a buffered output, so it still has issues associated with unbuffered inputs.

 

I questioned it because RCA's stated method for creating buffered logic from unbuffered was to De Morganize. The schematic I posted doesn't conform to their stated methodology.

How is that related to it being an OR gate and not a NOR gate?

 

How is that related to it being an OR gate and not a NOR gate?

Typo on my part. My point is that they said it was buffered, but the inputs aren't buffered.