Hello all,

can someone explain this circuit for both high and low inputs in Q18's base!

Thanks in advance!

View attachment 217367

It looks like a basic PMOS power switch. When Q18 base is high its collector pulls down the gate of the MOSFET via the resistive divider network and when that happens the drain of the MOSFET delivers the 12V to the output connector. When the base of Q18 is low the gate and source of the MOSFET are sitting at 12V so the drain does not see the 12V. The reason for the zener between the gate is to limit the maximum Vgs that the MOSFET can exceed. Basically, this circuit is just a solid state switch for the 12V

 

If it were just a switch, then why the LC filter on the output? Obviously a PWM circuit.