***VregenZ pin on piccolo controller***

Discussion in 'General Electronics Chat' started by artmaster547, Nov 30, 2016.

  1. artmaster547

    Thread Starter Member

    Jan 6, 2016
    398
    7
    Hi all I need some advice about a specific pin on the following controller:TMS320F28035PAG, I have attached the datasheet with this thread. Do I need to connect pin 60, VREGENZ, up to GND, and also with VDD what connections should I then be making can I connect VDD to 3V3 and just add 2u2 caps to each Vdd pin?
    Kind regards
    Sunday
     
  2. wayneh

    Expert

    Sep 9, 2010
    15,000
    5,453
    The data sheet describes the function of the pin. Seems like you'd want to pull it to ground. My read of it is that you would then leave VDD open and use the capacitors on VDDIO and VDDA.

    VREGENZ Internal VREG Enable/Disable – pull low to enable VREG, pull high to disable VREG

    6.5.1

    Although the core and I/O circuitry operate on two different voltages, these devices have an on-chip voltage regulator (VREG) to generate the VDD voltage from the VDDIO supply. This eliminates the cost and space of a second external regulator on an application board. Additionally, internal power-on reset (POR) and brown-out reset (BOR) circuits monitor both the VDD and VDDIO rails during power-up and run mode.

    On-chip Voltage Regulator (VREG)

    A linear regulator generates the core voltage (VDD) from the VDDIO supply. Therefore, although capacitors are required on each VDD pin to stabilize the generated voltage, power need not be supplied to these pins to operate the device. Conversely, the VREG can be disabled, should power or redundancy be the primary concern of the application.

    6.5.1.1 Using the On-chip VREG

    To utilize the on-chip VREG, the VREGENZ pin should be tied low and the appropriate recommended operating voltage should be supplied to the VDDIO and VDDA pins. In this case, the VDD voltage needed by the core logic will be generated by the VREG. Each VDD pin requires on the order of 1.2 μF (minimum) capacitance for proper regulation of the VREG. These capacitors should be located as close as possible to the VDD pins.

    6.5.1.2 Disabling the On-chip VREG

    To conserve power, it is also possible to disable the on-chip VREG and supply the core logic voltage to the VDD pins with a more efficient external regulator. To enable this option, the VREGENZ pin must be tied high.​
     
Loading...