I'm having trouble getting a negative voltage out of a positive power supply and then regulating that for various loads.

It should be within -4.5V to -6V using a +5V power-supply. There are two methods for this, I went with charge-pump over buck-boost. I simulated the circuit before implementing, and needless to say I didn't quite reach -4.5V in practice, (it reached about -4.2V)

With that reached I tried to use a LM324N op-amp as a unity gain op-amp to regulate the voltage but it didn't work as I found out later it doesn't swing to the negative side. I also need to work out a way to make it more negative than the current -4.2V

Any help greatly appreciated!

 

The first thing is to understand why your output is only going to -4.2V.

Describe what you expect the voltages to be at each of the nodes starting with the junction of the two transistors, and moving to the right, at each subsequent nodes. Do this for each phase of the output of the 555 (which is what I assume your block is, though you really should identify it).

As for regulation using the LM324, there's no way we can make any observations regarding that unless you show how you had it hooked up. We are not mind readers.

 

Hi CircuitZord,

If you think that -4.2V isn't going to cut the mustard just wait until you put a load on the output.

As WBahn suggests, do the analysis and then perhaps try an alternative solution. Such as the boost converter idea you discarded.

 

Hmm, well the reason it's going to -4.2V and not -4.5V or -5V as the simulation suggests is simply because it assumes ideal wires (0 resistance), I don't have long wires running around my circuit, but there are quite a few and there is resistance in the circuit not modeled in the simulation that's causing the drop.

Yes, it is a 555 timer.

I'd like to know if I use a single-rail op-amp such as an LM324 and power it with a +5V rail like the circuit is run with, will I never be able to get an output that's negative? I'm not going with buck-boost at the moment because I've already spent a few days with the charge-pump so I don't want to revert to a new topology, maybe if I get this right I will consider learning a new one.

 

Even if you were able to get an Lm324 based regulator running its output will only swing to within 1.5V of the positive or negative supply rail. So you would need to generate negative 6.5V to get a negative 5V nominal regulated output.

 

Yea that's what I've just found out now, the regulation with the op-amp alone is a no-go. What do you suggest I should do?

 

I guess while you are resolved to stick with the charge pump your options aren't great.

 

Well, what would be some options?

 

Hmm, well the reason it's going to -4.2V and not -4.5V or -5V as the simulation suggests is simply because it assumes ideal wires (0 resistance), I don't have long wires running around my circuit, but there are quite a few and there is resistance in the circuit not modeled in the simulation that's causing the drop.

Nope, that's not the reason.

Analyze the circuit.

Let's consider a situation in which the voltage on the output node is at it's final value of Vout. Let's call the node just to the left of Vout V1 and the node to the left of that V2 (the node with the junction of the two transistor collectors).

The output of the 555 has just changed such that V2 is now at its highest value.

Q1) In terms of Vcc and Vbe, what is the voltage on V2 at this point?

Q2) In terms of Vd, the forward bias drop of the diode, what is the voltage at V1?

Now the 555 changes state and V2 transitions downward.

Q3) Assuming that no current flows (a bad assumption, but let's go with it), what is the voltage at V2 after the transition (again in terms of Vcc and Vbe)?

Q4) What is the voltage at V1?

Q5) What is the voltage at Vout, assuming that the diode is just barely forward biased by Vd?

Q6) Now, let's assume that Vbe=Vd, what is Vout in terms of Vcc and Vd?

Q7) What does Vd have to be in order order for Vout to be -4.2V if Vcc is 5V?

Q8) Is it reasonable to expect Vout to be much less than -4.2V?

Now consider that, if there is a load of any kind, you will need current flowing in the transistors and diodes, so just barely forward biasing them won't cut it.

Q9) If Vbe=Vd=0.7V, what would Vout be?

 

Q1) In terms of Vcc and Vbe, what is the voltage on V2 at this point?

It should be whatever voltage is at the base - 0.7V. In practice what's coming out of the 555 timer is like around 3.6V at its highest

Q2) In terms of Vd, the forward bias drop of the diode, what is the voltage at V1?

I am not too sure.

Now the 555 changes state and V2 transitions downward.

Q3) Assuming that no current flows (a bad assumption, but let's go with it), what is the voltage at V2 after the transition (again in terms of Vcc and Vbe)?

It will be 0V if no current flows as then there's no voltage drop across the resistor and hence VB = 0V.

Q4) What is the voltage at V1?

Not sure.

Q5) What is the voltage at Vout, assuming that the diode is just barely forward biased by Vd?

Q6) Now, let's assume that Vbe=Vd, what is Vout in terms of Vcc and Vd?

Q7) What does Vd have to be in order order for Vout to be -4.2V if Vcc is 5V?

Q8) Is it reasonable to expect Vout to be much less than -4.2V?

No idea!

 

It should be whatever voltage is at the base - 0.7V. In practice what's coming out of the 555 timer is like around 3.6V at its highest

Well, that's gonna be a problem!

If you are only getting to 3.6V, then I don't see how you are getting -4.2V at the output at all.

Let's use Vhi as the output of the 555 when it is outputting a HI level. Let's use Vlo as the output when it is outputting a LO level.

When the output is HI, the top transistor is nominally on with a base voltage of Vhi and then V1 would have a voltage of

V1H = Vhi - Vbe

Let's not assume that Vbe is 0.7V because it will be much lower than that when the currents are very small. So let's just call it Vbe.

The voltage at V2 will be clamped by the diode to ground at Vd. Again, let's not assume that the forward voltage drop is 0.7V and, instead, just call it Vd.

V2H = Vd

When the 555 transitions from HI to LO, the voltage on V1 will go to

V1L = Vlo + Vbe

The change in voltage will be

ΔV1 = V1H - V1L = (Vhi-Vbe) - (Vlo+Vbe) = (Vhi-Vlo) - 2Vbe

The voltage at V2, if the capacitor holds its charge, drops by this same amount:

V2L = V2H - ΔV1
V2L = Vd - [(Vhi-Vlo) - 2Vbe]
V2L = -(Vhi-Vlo) + (Vd + 2Vbe)

The output voltage will, if there is no load current, stabilize at one diode drop above V2L, or

Vout = V2L + Vd

Vout = -(Vhi-Vlo) + 2(Vd + Vbe)

If there is no load current and negligible leakage current, then the system will stabilize at a point in which

Vd = Vbe ≈ 0V

Thus, the best you can hope for, is

Vout = -(Vhi - Vlo)

If your Vhi is only 3.6V and, assuming your Vlo is about 0V, then you should be seeing, at best, -3.6V. I don't know why you are seeing -4.2V. I was assuming that your 555 was outputting something much closer to 5V.

Now, if you have any load current at all, then your Vbe and Vd values quickly approach the 0.5V to 0.7V range and your steady state average Vout is reduced (in magnitude) by something around 2.5V.

 

Firstly, WBahn, thanks for your patience and explanations.

I must add that when I first posted this I had done this in the lab at uni where the power-supply is a lot better. I did indeed get -4.2V, some people employing a similar circuit (if not exactly the same) achieved this too.

My 3.6V 555 ouput high I just got at home today, I've got a shoddy old computer PSU which has some nasty ripple. It's reporting Vmax at 4.92V and Vmin at 4.84V which I figured was enough for initial purposes.

I do not know what my 555 was sending out in the uni lab, but it would have been higher with a more stable 5V Vcc.

What are my options to make the voltage more negative?

My home attempts have been pretty poor, I just got -2.96V to -3V today :S without the transistors, and around -2.5V with the transistors. I'm not sure why my results are so variable.

 

The attached simulation schematic is my attempt at a Dickson Charge Pump using the 555 timer. It produces an output of around +6V in the configuration shown. It's likely with a bit of fiddling you could get a higher voltage at the output. Depends on how much load is envisaged. Driving the first switched capacitor from the full 0 to 5V range is the challenge.

You may be able to think of a method of creating a negative output from this system, but I haven't thought too much about it - other than imagining an additional charge pump similar to your original schematic.

 

Hey, thanks for the response. I'm just about too look at your schematic, but this is exactly what I've been working on. I so far managed to get ~-3.5V output, but I ran out of electrolytic caps and diodes to extend the multiplier, going to grab them first thing in the morning!

 

Hmm, interesting, I'm going to simulate that and see what I can modify.

Mine's a bit different, I'm using the 555 timer to drive the base of an NPN to get a bigger gain on the clock voltage, and then feeding that into an array of caps and diodes. It's working so far, but will need more work on the voltage regulation later on.

 

You"ll also note significant improvement if you use Schottky diodes rather than Silicon types.

 

I have redesigned the circuit and can easily get the voltage ranges I want from -1V to -16V no problems, however what is the biggest problem is the output current.

I measured the current at the output at around 5uA. in my actual circuit. Any load will pretty much render this useless so I need to integrate some type of feedback mechanism. What should I do from here?

I thought of amplifying the current using a darlington pair (PNP) which works in simulation, however it increases my output voltage to around +1.5V if I couple it to the output, so now I'm stuck.

Here is the new circuit:

It's basically a 555 timer generating a clock, amplifying the clock signal with an NPN transistor, and then using a Dickson multiplier charge pump to progressively step down the voltage.

Because of the switching nature of the clock, it's causing the power-supply to exhibit some switching pulses too. So I put some decoupling capacitors between the outputs of the two clocks to reduce this somewhat. I've got it around 150mV pk-pk which I aim to reduce even further later on.

 

You"ll also note significant improvement if you use Schottky diodes rather than Silicon types.

Yep, I am going to be using some schottky diodes to improve the performance.

 

I have been able to obtain a notional 25mA at -5V regulated in simulation - as per attached schematic. I used a CMOS oscillator rather than 555 Timer. With a Hex inverter chip all the gates could be on the same IC. All diodes are Schottky type.

No doubt one can do this with capacitive charge pump approach but with the introduction of some magnetics one could probably have a far simpler solution.