Voltage Regulator Margining using PWM for Dynamic Voltage Scaling

Thread Starter

loonytunes

Joined Feb 1, 2019
2
I'm trying to adjust the voltage output of a regulator dynamically using a PWM signal from the MCU. I came across this circuit online, and that implements what I'm trying to do but I am having difficulty understanding how its doing it. Is someone able to explain this circuit to me?

I know how to set a static voltage output of a regulator, by using the voltage divider, back into the FeedBack pin of the regulator. But the rest of the circuit to the right is confusing me.

I need to be able to dynamically control the output voltage from 0.69V to 0.89V, by using a PWM signal from an MCU.

Any help is appreciated!

Circuit_loonytunes-01.jpg
 

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danadak

Joined Mar 10, 2018
3,793
The PWM is changing the V seen by the fdbk pin on regulator. Not sure
why the 10K from PWM output to Vregout, may have used open drain
ouput at MCU.

The PWM output is converted to DC V by 1 nF and 160K. That V is then
used to incrementally change the fdbk pin V.

How the designer got the other R values unsure what he was computing,
parameters.

What is the reg out you want and what range do you wish PWM to change
at the fdbk pin ?


Regards, Dana.
 

Thread Starter

loonytunes

Joined Feb 1, 2019
2
The PWM is changing the V seen by the fdbk pin on regulator. Not sure
why the 10K from PWM output to Vregout, may have used open drain
ouput at MCU.

The PWM output is converted to DC V by 1 nF and 160K. That V is then
used to incrementally change the fdbk pin V.

How the designer got the other R values unsure what he was computing,
parameters.

What is the reg out you want and what range do you wish PWM to change
at the fdbk pin ?


Regards, Dana.
Thanks Dana for the reply.
The voltage out i want is between 0.69V-0.89V, and the feedback voltage is 0.6V just like in the circuit. But what i want to understand is how to calculate those values for the resistors and capacitor to give that output. I want to know what the calculations are to design this kind of circuit?
 

danadak

Joined Mar 10, 2018
3,793
upload_2019-2-1_20-40-58.png

I think approach is at 1 nF cap node we can consider that a V source. So its V
is PWM duty cycle factor x its Vdd.

Then we know what the FB vs reg output relationship is, from reg datasheet.
So one solves for the incremental current delivered by the 300 K into the 137K,
thereby lifting/dropping reg output thru its fdbk equation. Its a tedious nodal
analysis.

Regards, Dana.
 
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