Hello,
I have a question concerning how voltage level shifting works. I am using a light sensing device TSOP4838 from Vishay. This device is connected to a 5VDC power source and its output is an 38 KHZ alternating signal aprroximately 5VDC (4.7VDC). At default, when the sensor is not detecting anything, it outputs a constant 5VDC.
I need to feed the output signal of the TSOP4838 (5VDC)to a CPLD which only accepts 3.3 VDC input.
I am using the MAXII, EPM240 CPLD from Altera and they show a sample on how to interface a 5VDC signal or voltage level to a 3.3VDC input of a CPLD.
As you can view my attached schematic AAC_SCHEMATIC.doc, which shows my circuit, I was just wondering mathematically how and why it works.
You can view Altera's sample which starts on p. 8-7 of the AAC_max2_mii51009[1].pdf attachment. On p. 8-8 of this document, they speak of IOH. The IOH specification can be found on p.6 of 32 of the AAC_max2_mii51005[1].pdf attachment.
When the TSOP4838 is outputing the 5VDC, the internal transistor of TSOP4838 not forward biased (See TSOP4838 spec), and the current is actually going from the 5VDC supply (Pin 3 of the TSOP4838) and through an internal
30K resistor and through R2 and then through the clamping diode. How is it that at this instance I read 0.13ma????
Using ohms law, I don't see how this current causes the necessary voltage drop of 1.7VDC?
Any help as to why my circuit actually works is very appreciated.
With regards
Robert
I have a question concerning how voltage level shifting works. I am using a light sensing device TSOP4838 from Vishay. This device is connected to a 5VDC power source and its output is an 38 KHZ alternating signal aprroximately 5VDC (4.7VDC). At default, when the sensor is not detecting anything, it outputs a constant 5VDC.
I need to feed the output signal of the TSOP4838 (5VDC)to a CPLD which only accepts 3.3 VDC input.
I am using the MAXII, EPM240 CPLD from Altera and they show a sample on how to interface a 5VDC signal or voltage level to a 3.3VDC input of a CPLD.
As you can view my attached schematic AAC_SCHEMATIC.doc, which shows my circuit, I was just wondering mathematically how and why it works.
You can view Altera's sample which starts on p. 8-7 of the AAC_max2_mii51009[1].pdf attachment. On p. 8-8 of this document, they speak of IOH. The IOH specification can be found on p.6 of 32 of the AAC_max2_mii51005[1].pdf attachment.
When the TSOP4838 is outputing the 5VDC, the internal transistor of TSOP4838 not forward biased (See TSOP4838 spec), and the current is actually going from the 5VDC supply (Pin 3 of the TSOP4838) and through an internal
30K resistor and through R2 and then through the clamping diode. How is it that at this instance I read 0.13ma????
Using ohms law, I don't see how this current causes the necessary voltage drop of 1.7VDC?
Any help as to why my circuit actually works is very appreciated.
With regards
Robert
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